forked from M-Labs/artiq
ddb_temp: select appropriate compiler target
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531670d6c5
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@ -11,7 +11,7 @@ from artiq.language.units import *
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from artiq.compiler.module import Module
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from artiq.compiler.embedding import Stitcher
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from artiq.compiler.targets import RISCVTarget, CortexA9Target
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from artiq.compiler.targets import RV32IMATarget, RV32GTarget, CortexA9Target
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from artiq.coredevice.comm_kernel import CommKernel, CommKernelDummy
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# Import for side effects (creating the exception classes).
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@ -71,11 +71,13 @@ class Core:
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"core", "ref_period", "coarse_ref_period", "ref_multiplier",
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}
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def __init__(self, dmgr, host, ref_period, ref_multiplier=8, target="riscv"):
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def __init__(self, dmgr, host, ref_period, ref_multiplier=8, target="rv32g"):
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self.ref_period = ref_period
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self.ref_multiplier = ref_multiplier
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if target == "riscv":
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self.target_cls = RISCVTarget
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if target == "rv32g":
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self.target_cls = RV32GTarget
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elif target == "rv32ima":
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self.target_cls = RV32IMATarget
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elif target == "cortexa9":
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self.target_cls = CortexA9Target
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else:
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@ -11,14 +11,16 @@ from artiq.coredevice import jsondesc
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def process_header(output, description):
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if description["target"] not in ("kasli", "kasli_soc"):
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if description["target"] == "kasli":
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if description["hw_rev"] in ("v1.0", "v1.1"):
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cpu_target = "rv32ima"
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else:
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cpu_target = "rv32g"
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elif description["target"] == "kasli_soc":
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cpu_target = "cortexa9"
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else:
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raise NotImplementedError
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cpu_target = {
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"kasli": "riscv",
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"kasli_soc": "cortexa9"
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}[description["target"]]
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print(textwrap.dedent("""
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# Autogenerated for the {variant} variant
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core_addr = "{core_addr}"
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