Jack-Zheng
|
f796eedc08
|
PCB: fix grand dead zones
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2021-06-30 15:24:25 +08:00 |
Jack-Zheng
|
4853b02184
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PCB: replace 0201 resistors to 0402 as JLC cannot do SMT for 0201
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2021-06-30 14:59:13 +08:00 |
Jack-Zheng
|
93ba0cbe9d
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HSADC: change from AC coupling to DC coupling; PCB: finish HSADC layout
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2021-06-30 14:51:30 +08:00 |
Jack-Zheng
|
17127387c9
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PCB: optimize buck converter and shunt resistor layout
|
2021-06-30 11:36:53 +08:00 |
Jack-Zheng
|
26d727f8c5
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PCB: replace LVDS resistors with 0201 package, optimize LVDS pairs layout
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2021-06-29 16:49:26 +08:00 |
Jack-Zheng
|
8ffd698079
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PCB: optimize HSADC layout
|
2021-06-29 10:38:12 +08:00 |
Jack-Zheng
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6584f44f2a
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PCB: fix GND polygon dead zones; all: export BOM
|
2021-06-29 10:26:02 +08:00 |
Jack-Zheng
|
10818a4771
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PCB: fix small LVDS connection issue
|
2021-06-28 15:49:33 +08:00 |
Jack-Zheng
|
a16bee581b
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PCB: fix small LVDS connection issue
|
2021-06-28 15:45:06 +08:00 |
Jack-Zheng
|
185f9eacda
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PCB: finish routing
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2021-06-28 15:40:16 +08:00 |
Jack-Zheng
|
53accc8761
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PCB: finish IO and analog connectors
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2021-06-28 10:40:21 +08:00 |
Jack-Zheng
|
4b15f466a0
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PCB: finish SWD, IIC
|
2021-06-25 18:15:56 +08:00 |
Jack-Zheng
|
0e1120d266
|
FPGA: modify pin connections for convenient layout routing; PCB: finish FPGA IO, FSMC, ADC BUS, Power routing
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2021-06-25 16:57:46 +08:00 |
Jack-Zheng
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2a31c8b3f3
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PCB: finish LVDS routing
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2021-06-24 15:43:31 +08:00 |
Jack-Zheng
|
37941bfc2c
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PCB: finalize component positions and define board shape
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2021-06-22 17:14:32 +08:00 |
Jack-Zheng
|
6535ff5423
|
LVDS&IO: add fpga flash config; all: fix connection bugs; PCB: initialize component positions and layout
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2021-06-22 16:34:02 +08:00 |
Jack-Zheng
|
1df738664f
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all: update gitignore; remove redundant files
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2021-06-22 09:44:50 +08:00 |
Jack-Zheng
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982fefd6b5
|
all: update gitigore to fix symbol and footpin bugs; replace messy libs into one
|
2021-06-21 16:05:17 +08:00 |
Jack-Zheng
|
9bcc9a229b
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TestAutomation: replace messy wires with bus
|
2021-06-21 12:10:31 +08:00 |
Jack-Zheng
|
dfe4255a21
|
MCU: finish FSMC, PWM
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2021-06-17 10:52:33 +08:00 |
Jack-Zheng
|
5b4801ff74
|
FPGA: finish EEM, I2C, CFG, SPI FLASH
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2021-06-16 17:32:33 +08:00 |
Jack-Zheng
|
fc2cb47610
|
all: map symbol and footpins
|
2021-06-16 17:32:33 +08:00 |
Jack-Zheng
|
da19dad9cd
|
init project
|
2021-06-16 17:31:36 +08:00 |