Merge pull request #3 from quartiq/release/0.3.0

Prepping for release
Reverting repo update
2023-07-03 14:51:20 +02:00 · 2023-07-03 14:48:02 +02:00 · 2023-07-03 13:50:06 +02:00 · 2023-07-03 13:45:28 +02:00 · 2023-07-03 13:43:12 +02:00 · 2023-07-03 13:39:50 +02:00
14 changed files with 585 additions and 859 deletions
--- a/.github/workflows/ci.yml
+++ b/.github/workflows/ci.yml
@ -0,0 +1,117 @@
+name: Continuous Integration
+
+on:
+  push:
+    branches: [master]
+
+  pull_request:
+    branches: [master]
+
+env:
+  CARGO_TERM_COLOR: always
+
+jobs:
+  style:
+    runs-on: ubuntu-latest
+    steps:
+      - uses: actions/checkout@v2
+      - uses: actions-rs/toolchain@v1
+        with:
+          profile: minimal
+          toolchain: stable
+          override: true
+          components: rustfmt
+
+      - name: Style Check
+        uses: actions-rs/cargo@v1
+        with:
+          command: fmt
+          args: --all -- --check
+
+  clippy:
+    runs-on: ubuntu-latest
+    steps:
+      - uses: actions/checkout@v2
+
+      - uses: actions-rs/toolchain@v1
+        with:
+          profile: minimal
+          toolchain: stable
+          target: thumbv7em-none-eabihf
+          override: true
+          components: clippy
+
+      - name: Clippy Check
+        uses: actions-rs/cargo@v1
+        with:
+          command: clippy
+          args: --all-features
+
+  documentation:
+    runs-on: ubuntu-latest
+    steps:
+      - uses: actions/checkout@v2
+
+      - uses: actions-rs/toolchain@v1
+        with:
+          profile: minimal
+          toolchain: stable
+          target: thumbv7em-none-eabihf
+          override: true
+
+      - name: Cargo Doc
+        uses: actions-rs/cargo@v1
+        with:
+          command: doc
+          args: --all-features
+
+  audit:
+    runs-on: ubuntu-latest
+    steps:
+      - uses: actions/checkout@v2
+      - name: Cargo Audit
+        uses: actions-rs/audit-check@v1
+        with:
+          token: ${{ secrets.GITHUB_TOKEN }}
+
+  compile:
+    runs-on: ubuntu-latest
+    strategy:
+      matrix:
+        toolchain:
+          - stable
+          - beta
+
+    steps:
+      - uses: actions/checkout@v2
+
+      - name: Install Rust ${{ matrix.toolchain }}
+        uses: actions-rs/toolchain@v1
+        with:
+          toolchain: ${{ matrix.toolchain }}
+          target: thumbv7em-none-eabihf
+          override: true
+
+      - name: Cargo Check
+        uses: actions-rs/cargo@v1
+        with:
+          command: check
+          args: --verbose --all-features
+
+      - name: Cargo Build
+        uses: actions-rs/cargo@v1
+        with:
+          command: build
+          args: --all-features
+
+      - name: Cargo Build [Release]
+        uses: actions-rs/cargo@v1
+        with:
+          command: build
+          args: --release --all-features
+
+      - name: Cargo Build [Examples]
+        uses: actions-rs/cargo@v1
+        with:
+          command: build
+          args: --examples --all-features
--- a/.gitignore
+++ b/.gitignore
@ -0,0 +1,2 @@
+/target
+Cargo.lock
--- a/Cargo.lock
+++ b/Cargo.lock
@ -1,417 +0,0 @@
-# This file is automatically @generated by Cargo.
-# It is not intended for manual editing.
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--- a/Cargo.toml
+++ b/Cargo.toml
@ -1,9 +1,9 @@
 [package]
 categories = ["embedded", "no-std"]
 name = "enc424j600"
-description = "Embbeded Rust Ethernet driver for ENC424J600 Ethernet controller with SPI interface, compatible with STM32F4xx"
-authors = ["Harry Ho <hh@m-labs.hk>"]
-version = "0.1.0"
+description = "Embbeded Rust Ethernet driver for ENC424J600 Ethernet controller with SPI interface"
+authors = ["Harry Ho <hh@m-labs.hk>", "Dip Cheung <dc@m-labs.hk>"]
+version = "0.3.0"
 keywords = ["ethernet", "eth", "enc424j600", "stm32", "stm32f4xx"]
 repository = "https://git.m-labs.hk/M-Labs/ENC424J600"
 edition = "2018"
@ -13,33 +13,30 @@ license = "BSD-2-Clause"
 volatile-register = "0.2"
 aligned = "0.3"
 embedded-hal = "0.2"
-smoltcp = { version = "0.6.0", default-features = false, features = ["proto-ipv4", "proto-ipv6", "socket-icmp", "socket-udp", "socket-tcp", "log", "verbose", "ethernet"], optional = true }
+smoltcp = { version = "0.7.0", default-features = false, features = [ "socket-raw", "proto-ipv4",
+    "proto-ipv6", "socket-tcp", "ethernet"], optional = true }
+cortex-m = {version = "0.5", optional = true }
+
 # Optional dependencies for building examples
-stm32f4xx-hal = { version = "0.8", optional = true }
-cortex-m = { version = "0.5", optional = true }
-cortex-m-rt = { version = "0.6", optional = true }
-cortex-m-rtic = { version = "0.5.3", optional = true }
-panic-itm = { version = "0.4", optional = true }
-log = { version = "0.4", optional = true }
+[dev-dependencies]
+stm32f4xx-hal = { version = "0.8", features = ["stm32f407", "rt"] }
+cortex-m-rt = "0.6"
+cortex-m-rtic = "0.5.3"
+panic-itm = "0.4"
+log = "0.4"

 [features]
 smoltcp-phy = ["smoltcp"]
-smoltcp-phy-all = [
-    "smoltcp/socket-raw", "smoltcp/socket-udp", "smoltcp/socket-tcp",
-    "smoltcp/proto-ipv4", "smoltcp/proto-ipv6"
-]
-# Example-based features
-tx_stm32f407 = ["stm32f4xx-hal/stm32f407", "cortex-m", "cortex-m-rtic", "panic-itm", "log"]
-tcp_stm32f407 = ["stm32f4xx-hal/stm32f407", "cortex-m", "cortex-m-rt", "cortex-m-rtic", "smoltcp-phy-all", "smoltcp/log", "panic-itm", "log"]
+cortex-m-cpu = ["cortex-m"]
 default = []

 [[example]]
 name = "tx_stm32f407"
-required-features = ["tx_stm32f407"]
+required-features = ["smoltcp", "cortex-m-cpu"]

 [[example]]
 name = "tcp_stm32f407"
-required-features = ["tcp_stm32f407"]
+required-features = ["smoltcp", "cortex-m-cpu"]

 [profile.release]
 codegen-units = 1
--- a/examples/tcp_stm32f407.rs
+++ b/examples/tcp_stm32f407.rs
@ -2,43 +2,31 @@
 #![no_main]

 extern crate panic_itm;
-use cortex_m::{iprintln, iprint};
+use cortex_m::{iprint, iprintln};

-use embedded_hal::{
-    digital::v2::OutputPin,
-    blocking::delay::DelayMs
-};
+use embedded_hal::{blocking::delay::DelayMs, digital::v2::OutputPin};
+use enc424j600::smoltcp_phy;
 use stm32f4xx_hal::{
-    rcc::RccExt,
-    gpio::GpioExt,
-    time::U32Ext,
-    stm32::ITM,
-    delay::Delay,
-    spi::Spi,
-    time::Hertz
+    delay::Delay, gpio::GpioExt, rcc::RccExt, spi::Spi, stm32::ITM, time::Hertz, time::U32Ext,
 };
-use enc424j600;
-use enc424j600::{smoltcp_phy, EthController};

-use smoltcp::wire::{
-    EthernetAddress, IpAddress, IpCidr, Ipv6Cidr
-};
-use smoltcp::iface::{NeighborCache, EthernetInterfaceBuilder, EthernetInterface};
-use smoltcp::socket::{SocketSet, TcpSocket, TcpSocketBuffer};
-use core::str;
 use core::fmt::Write;
+use core::str;
+use smoltcp::iface::{EthernetInterface, EthernetInterfaceBuilder, NeighborCache};
+use smoltcp::socket::{SocketSet, TcpSocket, TcpSocketBuffer};
+use smoltcp::wire::{EthernetAddress, IpAddress, IpCidr, Ipv6Cidr};

 /// Timer
 use core::cell::RefCell;
 use cortex_m::interrupt::Mutex;
 use cortex_m_rt::exception;
+use smoltcp::time::Instant;
 use stm32f4xx_hal::{
    rcc::Clocks,
+    stm32::SYST,
    time::MilliSeconds,
-    timer::{Timer, Event as TimerEvent},
-    stm32::SYST
+    timer::{Event as TimerEvent, Timer},
 };
-use smoltcp::time::Instant;
 /// Rate in Hz
 const TIMER_RATE: u32 = 20;
 /// Interval duration in milliseconds
@ -56,31 +44,35 @@ fn timer_setup(syst: SYST, clocks: Clocks) {
 #[exception]
 fn SysTick() {
    cortex_m::interrupt::free(|cs| {
-        *TIMER_MS.borrow(cs)
-            .borrow_mut() += TIMER_DELTA;
+        *TIMER_MS.borrow(cs).borrow_mut() += TIMER_DELTA;
    });
 }

 /// Obtain current time in milliseconds
 pub fn timer_now() -> MilliSeconds {
-    let ms = cortex_m::interrupt::free(|cs| {
-        *TIMER_MS.borrow(cs)
-            .borrow()
-    });
+    let ms = cortex_m::interrupt::free(|cs| *TIMER_MS.borrow(cs).borrow());
    ms.ms()
 }

 ///
 use stm32f4xx_hal::{
-    stm32::SPI1,
    gpio::{
-        gpioa::{PA5, PA6, PA7, PA4},
-        Alternate, AF5, Output, PushPull
-    }
+        gpioa::{PA4, PA5, PA6, PA7},
+        Alternate, Output, PushPull, AF5,
+    },
+    stm32::SPI1,
 };
-type BoosterSpiEth = enc424j600::SpiEth<
-    Spi<SPI1, (PA5<Alternate<AF5>>, PA6<Alternate<AF5>>, PA7<Alternate<AF5>>)>,
-    PA4<Output<PushPull>>>;
+type SpiEth = enc424j600::Enc424j600<
+    Spi<
+        SPI1,
+        (
+            PA5<Alternate<AF5>>,
+            PA6<Alternate<AF5>>,
+            PA7<Alternate<AF5>>,
+        ),
+    >,
+    PA4<Output<PushPull>>,
+>;

 pub struct NetStorage {
    ip_addrs: [IpCidr; 1],
@ -89,21 +81,15 @@ pub struct NetStorage {

 static mut NET_STORE: NetStorage = NetStorage {
    // Placeholder for the real IP address, which is initialized at runtime.
-    ip_addrs: [IpCidr::Ipv6(
-        Ipv6Cidr::SOLICITED_NODE_PREFIX,
-    )],
+    ip_addrs: [IpCidr::Ipv6(Ipv6Cidr::SOLICITED_NODE_PREFIX)],
    neighbor_cache: [None; 8],
 };

 #[rtic::app(device = stm32f4xx_hal::stm32, peripherals = true, monotonic = rtic::cyccnt::CYCCNT)]
 const APP: () = {
    struct Resources {
-        eth_iface: EthernetInterface<
-            'static,
-            'static,
-            'static,
-            smoltcp_phy::SmoltcpDevice<BoosterSpiEth>>,
-        itm: ITM
+        eth_iface: EthernetInterface<'static, smoltcp_phy::SmoltcpDevice<SpiEth>>,
+        itm: ITM,
    }

    #[init()]
@ -115,7 +101,10 @@ const APP: () = {
        c.core.DWT.enable_cycle_counter();
        c.core.DCB.enable_trace();

-        let clocks = c.device.RCC.constrain()
+        let clocks = c
+            .device
+            .RCC
+            .constrain()
            .cfgr
            .sysclk(168.mhz())
            .hclk(168.mhz())
@ -128,8 +117,7 @@ const APP: () = {
        let mut itm = c.core.ITM;
        let stim0 = &mut itm.stim[0];

-        iprintln!(stim0,
-            "Eth TCP Server on STM32-F407 via NIC100/ENC424J600");
+        iprintln!(stim0, "Eth TCP Server on STM32-F407 via NIC100/ENC424J600");

        // NIC100 / ENC424J600 Set-up
        let spi1 = c.device.SPI1;
@ -149,15 +137,18 @@ const APP: () = {
        let eth_iface = {
            let mut spi_eth = {
                let spi_eth_port = Spi::spi1(
-                    spi1, (spi1_sck, spi1_miso, spi1_mosi),
+                    spi1,
+                    (spi1_sck, spi1_miso, spi1_mosi),
                    enc424j600::spi::interfaces::SPI_MODE,
                    Hertz(enc424j600::spi::interfaces::SPI_CLOCK_FREQ),
-                    clocks);
-                enc424j600::SpiEth::new(spi_eth_port, spi1_nss)
+                    clocks,
+                );
+
+                SpiEth::new(spi_eth_port, spi1_nss).cpu_freq_mhz(168)
            };

            // Init controller
-            match spi_eth.init_dev(&mut delay) {
+            match spi_eth.reset(&mut delay) {
                Ok(_) => {
                    iprintln!(stim0, "Initializing Ethernet...")
                }
@ -168,14 +159,14 @@ const APP: () = {

            // Read MAC
            let mut eth_mac_addr: [u8; 6] = [0; 6];
-            spi_eth.read_from_mac(&mut eth_mac_addr);
+            spi_eth.read_mac_addr(&mut eth_mac_addr);
            for i in 0..6 {
                let byte = eth_mac_addr[i];
                match i {
                    0 => iprint!(stim0, "MAC Address = {:02x}-", byte),
                    1..=4 => iprint!(stim0, "{:02x}-", byte),
                    5 => iprint!(stim0, "{:02x}\n", byte),
-                _ => ()
+                    _ => (),
                };
            }

@ -208,10 +199,7 @@ const APP: () = {
        timer_setup(delay.free(), clocks);
        iprintln!(stim0, "Timer initialized");

-        init::LateResources {
-            eth_iface,
-            itm
-        }
+        init::LateResources { eth_iface, itm }
    }

    #[idle(resources=[eth_iface, itm])]
@ -241,8 +229,11 @@ const APP: () = {
        let greet_handle = socket_set.add(greet_socket);
        {
            let store = unsafe { &mut NET_STORE };
-            iprintln!(stim0,
-                "TCP sockets will listen at {}", store.ip_addrs[0].address());
+            iprintln!(
+                stim0,
+                "TCP sockets will listen at {}",
+                store.ip_addrs[0].address()
+            );
        }

        // Copied / modified from:
@ -254,8 +245,7 @@ const APP: () = {
            let now = timer_now().0;
            let instant = Instant::from_millis(now as i64);
            match iface.poll(&mut socket_set, instant) {
-                Ok(_) => {
-                },
+                Ok(_) => {}
                Err(e) => {
                    iprintln!(stim0, "[{}] Poll error: {:?}", instant, e)
                }
@ -264,33 +254,40 @@ const APP: () = {
            {
                let mut socket = socket_set.get::<TcpSocket>(echo_handle);
                if !socket.is_open() {
-                    iprintln!(stim0,
-                        "[{}] Listening to port 1234 for echoing, time-out in 10s", instant);
+                    iprintln!(
+                        stim0,
+                        "[{}] Listening to port 1234 for echoing, time-out in 10s",
+                        instant
+                    );
                    socket.listen(1234).unwrap();
                    socket.set_timeout(Some(smoltcp::time::Duration::from_millis(10000)));
                }
                if socket.can_recv() {
-                    iprintln!(stim0,
-                    "[{}] Received packet: {:?}", instant, socket.recv(|buffer| {
-                        (buffer.len(), str::from_utf8(buffer).unwrap())
-                    }));
+                    iprintln!(
+                        stim0,
+                        "[{}] Received packet: {:?}",
+                        instant,
+                        socket.recv(|buffer| { (buffer.len(), str::from_utf8(buffer).unwrap()) })
+                    );
                }
            }
            // Control the "greeting" socket (:4321)
            {
                let mut socket = socket_set.get::<TcpSocket>(greet_handle);
                if !socket.is_open() {
-                    iprintln!(stim0,
+                    iprintln!(
+                        stim0,
                        "[{}] Listening to port 4321 for greeting, \
-                        please connect to the port", instant);
+                        please connect to the port",
+                        instant
+                    );
                    socket.listen(4321).unwrap();
                }

                if socket.can_send() {
                    let greeting = "Welcome to the server demo for STM32-F407!";
                    write!(socket, "{}\n", greeting).unwrap();
-                    iprintln!(stim0,
-                        "[{}] Greeting sent, socket closed", instant);
+                    iprintln!(stim0, "[{}] Greeting sent, socket closed", instant);
                    socket.close();
                }
            }
--- a/examples/tx_stm32f407.rs
+++ b/examples/tx_stm32f407.rs
@ -2,40 +2,38 @@
 #![no_main]

 extern crate panic_itm;
-use cortex_m::{iprintln, iprint};
+use cortex_m::{iprint, iprintln};

-use embedded_hal::{
-    digital::v2::OutputPin,
-    blocking::delay::DelayMs
-};
+use embedded_hal::{blocking::delay::DelayMs, digital::v2::OutputPin};
+use enc424j600::EthPhy;
 use stm32f4xx_hal::{
-    rcc::RccExt,
-    gpio::GpioExt,
-    time::U32Ext,
-    stm32::ITM,
-    delay::Delay,
-    spi::Spi,
-    time::Hertz
+    delay::Delay, gpio::GpioExt, rcc::RccExt, spi::Spi, stm32::ITM, time::Hertz, time::U32Ext,
 };
-use enc424j600;
-use enc424j600::EthController;

 ///
 use stm32f4xx_hal::{
-    stm32::SPI1,
    gpio::{
-        gpioa::{PA5, PA6, PA7, PA4},
-        Alternate, AF5, Output, PushPull
+        gpioa::{PA4, PA5, PA6, PA7},
+        Alternate, Output, PushPull, AF5,
    },
+    stm32::SPI1,
 };
-type BoosterSpiEth = enc424j600::SpiEth<
-    Spi<SPI1, (PA5<Alternate<AF5>>, PA6<Alternate<AF5>>, PA7<Alternate<AF5>>)>,
-    PA4<Output<PushPull>>>;
+type SpiEth = enc424j600::Enc424j600<
+    Spi<
+        SPI1,
+        (
+            PA5<Alternate<AF5>>,
+            PA6<Alternate<AF5>>,
+            PA7<Alternate<AF5>>,
+        ),
+    >,
+    PA4<Output<PushPull>>,
+>;

 #[rtic::app(device = stm32f4xx_hal::stm32, peripherals = true, monotonic = rtic::cyccnt::CYCCNT)]
 const APP: () = {
    struct Resources {
-        spi_eth: BoosterSpiEth,
+        spi_eth: SpiEth,
        delay: Delay,
        itm: ITM,
    }
@ -45,7 +43,10 @@ const APP: () = {
        c.core.SCB.enable_icache();
        c.core.SCB.enable_dcache(&mut c.core.CPUID);

-        let clocks = c.device.RCC.constrain()
+        let clocks = c
+            .device
+            .RCC
+            .constrain()
            .cfgr
            .sysclk(168.mhz())
            .hclk(168.mhz())
@ -59,8 +60,7 @@ const APP: () = {
        // Init ITM
        let mut itm = c.core.ITM;
        let stim0 = &mut itm.stim[0];
-        iprintln!(stim0,
-            "Eth TX Pinging on STM32-F407 via NIC100/ENC424J600");
+        iprintln!(stim0, "Eth TX Pinging on STM32-F407 via NIC100/ENC424J600");

        // NIC100 / ENC424J600 Set-up
        let spi1 = c.device.SPI1;
@ -78,15 +78,18 @@ const APP: () = {
        // Create SPI1 for HAL
        let mut spi_eth = {
            let spi_eth_port = Spi::spi1(
-                spi1, (spi1_sck, spi1_miso, spi1_mosi),
+                spi1,
+                (spi1_sck, spi1_miso, spi1_mosi),
                enc424j600::spi::interfaces::SPI_MODE,
                Hertz(enc424j600::spi::interfaces::SPI_CLOCK_FREQ),
-                clocks);
-            enc424j600::SpiEth::new(spi_eth_port, spi1_nss)
+                clocks,
+            );
+
+            SpiEth::new(spi_eth_port, spi1_nss).cpu_freq_mhz(168)
        };

        // Init
-        match spi_eth.init_dev(&mut delay) {
+        match spi_eth.reset(&mut delay) {
            Ok(_) => {
                iprintln!(stim0, "Initializing Ethernet...")
            }
@ -97,14 +100,14 @@ const APP: () = {

        // Read MAC
        let mut eth_mac_addr: [u8; 6] = [0; 6];
-        spi_eth.read_from_mac(&mut eth_mac_addr);
+        spi_eth.read_mac_addr(&mut eth_mac_addr);
        for i in 0..6 {
            let byte = eth_mac_addr[i];
            match i {
                0 => iprint!(stim0, "MAC Address = {:02x}-", byte),
                1..=4 => iprint!(stim0, "{:02x}-", byte),
                5 => iprint!(stim0, "{:02x}\n", byte),
-                _ => ()
+                _ => (),
            };
        }

@ -125,20 +128,20 @@ const APP: () = {
        let stim0 = &mut c.resources.itm.stim[0];
        // Testing Eth TX
        let eth_tx_dat: [u8; 64] = [
-            0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x08, 0x60,
-            0x6e, 0x44, 0x42, 0x95, 0x08, 0x06, 0x00, 0x01,
-            0x08, 0x00, 0x06, 0x04, 0x00, 0x01, 0x08, 0x60,
-            0x6e, 0x44, 0x42, 0x95, 0xc0, 0xa8, 0x01, 0x64,
-            0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xa8,
-            0x01, 0xe7, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-            0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-            0x00, 0x00, 0x00, 0x00, 0x69, 0xd0, 0x85, 0x9f
+            0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x08, 0x60, 0x6e, 0x44, 0x42, 0x95, 0x08, 0x06,
+            0x00, 0x01, 0x08, 0x00, 0x06, 0x04, 0x00, 0x01, 0x08, 0x60, 0x6e, 0x44, 0x42, 0x95,
+            0xc0, 0xa8, 0x01, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xa8, 0x01, 0xe7,
+            0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+            0x00, 0x00, 0x00, 0x00, 0x69, 0xd0, 0x85, 0x9f,
        ];
        loop {
            let mut eth_tx_packet = enc424j600::tx::TxPacket::new();
            eth_tx_packet.update_frame(&eth_tx_dat, 64);
-            iprint!(stim0,
-                "Sending packet (len={:}): ", eth_tx_packet.get_frame_length());
+            iprint!(
+                stim0,
+                "Sending packet (len={:}): ",
+                eth_tx_packet.get_frame_length()
+            );
            for i in 0..20 {
                let byte = eth_tx_packet.get_frame_byte(i);
                match i {
@ -149,10 +152,10 @@ const APP: () = {
                    13..=14 | 16..=18 => iprint!(stim0, "{:02x}", byte),
                    5 | 11 | 15 => iprint!(stim0, "{:02x} ", byte),
                    19 => iprint!(stim0, "{:02x} ...\n", byte),
-                    _ => ()
+                    _ => (),
                };
            }
-            c.resources.spi_eth.send_raw_packet(&eth_tx_packet);
+            c.resources.spi_eth.send_packet(&eth_tx_packet);
            iprintln!(stim0, "Packet sent");
            c.resources.delay.delay_ms(100_u32);
        }
--- a/nix/itm-tools.nix
+++ b/nix/itm-tools.nix
@ -1,21 +0,0 @@
-{ stdenv, fetchFromGitHub, rustPlatform, pkg-config }:
-
-rustPlatform.buildRustPackage rec {
-  version = "2019-11-15";
-  pname = "itm-tools";
-
-  src = fetchFromGitHub {
-    owner = "japaric";
-    repo = "itm-tools";
-    rev = "e94155e44019d893ac8e6dab51cc282d344ab700";
-    sha256 = "19xkjym0i7y52cfhvis49c59nzvgw4906cd8bkz8ka38mbgfqgiy";
-  };
-
-  cargoPatches = [ ./itm-tools-cargo-lock.patch ];
-
-  cargoSha256 = "0is702s14pgvd5i2m8aaw3zcsshqrwj97mjgg3wikbc627pagzg7";
-
-  nativeBuildInputs = [ pkg-config ];
-
-  doCheck = false;
-}
--- a/nix/rustPlatform.nix
+++ b/nix/rustPlatform.nix
@ -10,7 +10,7 @@ let
  ];
  rustChannel =
    lib.rustLib.fromManifestFile rustManifest {
-      inherit stdenv fetchurl patchelf;
+      inherit stdenv lib fetchurl patchelf;
    };
  rust =
    rustChannel.rust.override {
--- a/shell.nix
+++ b/shell.nix
@ -8,8 +8,6 @@ with pkgs;
 let
  rustPlatform = callPackage ./nix/rustPlatform.nix {};

-  itm-tools = callPackage ./nix/itm-tools.nix { inherit rustPlatform; };
-
  runHelp = writeShellScriptBin "run-help" ''
    echo "[Common Tools]"
    echo "  run-openocd-f4x"
@ -103,7 +101,7 @@ in
 stdenv.mkDerivation {
  name = "enc424j600-stm32-env";
  buildInputs = with rustPlatform.rust; [
-    rustc cargo pkgs.gdb pkgs.openocd pkgs.tmux itm-tools 
+    rustc cargo pkgs.gdb pkgs.openocd pkgs.tmux pkgs.itm-tools 
    runHelp runTmuxEnv killTmuxEnv
    runOpenOcdF4x runItmDemuxFollow
    exTxStm32f407 exTcpStm32f407
--- a/src/lib.rs
+++ b/src/lib.rs
@ -2,132 +2,175 @@

 pub mod spi;
 use embedded_hal::{
-    blocking::{
-        spi::Transfer,
-        delay::DelayUs,
-    },
+    blocking::{delay::DelayUs, spi::Transfer},
    digital::v2::OutputPin,
 };

 pub mod rx;
 pub mod tx;

-#[cfg(feature="smoltcp")]
+#[cfg(feature = "smoltcp")]
 pub mod smoltcp_phy;

 /// Max raw frame array size
-pub const RAW_FRAME_LENGTH_MAX: usize = 0x1000;
+pub const RAW_FRAME_LENGTH_MAX: usize = 1518;

-pub trait EthController {
-    fn init_dev(&mut self, delay: &mut impl DelayUs<u16>) -> Result<(), EthControllerError>;
-    fn init_rxbuf(&mut self) -> Result<(), EthControllerError>;
-    fn init_txbuf(&mut self) -> Result<(), EthControllerError>;
-    fn receive_next(&mut self, is_poll: bool) -> Result<rx::RxPacket, EthControllerError>;
-    fn send_raw_packet(&mut self, packet: &tx::TxPacket) -> Result<(), EthControllerError>;
-    fn set_promiscuous(&mut self) -> Result<(), EthControllerError>;
-    fn read_from_mac(&mut self, mac: &mut [u8]) -> Result<(), EthControllerError>;
+/// Trait representing PHY layer of ENC424J600
+pub trait EthPhy {
+    fn recv_packet(&mut self, is_poll: bool) -> Result<rx::RxPacket, Error>;
+    fn send_packet(&mut self, packet: &tx::TxPacket) -> Result<(), Error>;
 }

 /// TODO: Improve these error types
-pub enum EthControllerError {
+#[derive(Debug)]
+pub enum Error {
    SpiPortError,
-    GeneralError,
+    RegisterError,
    // TODO: Better name?
-    NoRxPacketError
+    NoRxPacketError,
 }

-impl From<spi::SpiPortError> for EthControllerError {
-    fn from(_: spi::SpiPortError) -> EthControllerError {
-        EthControllerError::SpiPortError
+impl From<spi::Error> for Error {
+    fn from(_: spi::Error) -> Error {
+        Error::SpiPortError
    }
 }

-/// Ethernet controller using SPI interface
-pub struct SpiEth<SPI: Transfer<u8>,
-                  NSS: OutputPin> {
+/// ENC424J600 controller in SPI mode
+pub struct Enc424j600<SPI: Transfer<u8>, NSS: OutputPin> {
    spi_port: spi::SpiPort<SPI, NSS>,
    rx_buf: rx::RxBuffer,
-    tx_buf: tx::TxBuffer
+    tx_buf: tx::TxBuffer,
 }

-impl <SPI: Transfer<u8>,
-      NSS: OutputPin> SpiEth<SPI, NSS> {
+impl<SPI: Transfer<u8>, NSS: OutputPin> Enc424j600<SPI, NSS> {
    pub fn new(spi: SPI, nss: NSS) -> Self {
-        SpiEth {
+        Enc424j600 {
            spi_port: spi::SpiPort::new(spi, nss),
            rx_buf: rx::RxBuffer::new(),
-            tx_buf: tx::TxBuffer::new()
+            tx_buf: tx::TxBuffer::new(),
        }
    }
-}

-impl <SPI: Transfer<u8>,
-      NSS: OutputPin> EthController for SpiEth<SPI, NSS> {
-    fn init_dev(&mut self, delay: &mut impl DelayUs<u16>) -> Result<(), EthControllerError> {
+    #[cfg(feature = "cortex-m-cpu")]
+    pub fn cpu_freq_mhz(mut self, freq: u32) -> Self {
+        self.spi_port = self.spi_port.cpu_freq_mhz(freq);
+        self
+    }
+
+    pub fn init(&mut self, delay: &mut impl DelayUs<u16>) -> Result<(), Error> {
+        self.reset(delay)?;
+        self.init_rxbuf()?;
+        self.init_txbuf()?;
+        Ok(())
+    }
+
+    pub fn reset(&mut self, delay: &mut impl DelayUs<u16>) -> Result<(), Error> {
        // Write 0x1234 to EUDAST
        self.spi_port.write_reg_16b(spi::addrs::EUDAST, 0x1234)?;
        // Verify that EUDAST is 0x1234
        let mut eudast = self.spi_port.read_reg_16b(spi::addrs::EUDAST)?;
        if eudast != 0x1234 {
-            return Err(EthControllerError::GeneralError)
+            return Err(Error::RegisterError);
        }
        // Poll CLKRDY (ESTAT<12>) to check if it is set
        loop {
            let estat = self.spi_port.read_reg_16b(spi::addrs::ESTAT)?;
-            if estat & 0x1000 == 0x1000 { break }
+            if estat & 0x1000 == 0x1000 {
+                break;
+            }
        }
-        // Set ETHRST (ECON2<4>) to 1
-        let econ2 = self.spi_port.read_reg_8b(spi::addrs::ECON2)?;
-        self.spi_port.write_reg_8b(spi::addrs::ECON2, 0x10 | (econ2 & 0b11101111))?;
-        // Wait for 25us
-        delay.delay_us(25_u16);
+        // Issue system reset - set ETHRST (ECON2<4>) to 1
+        self.spi_port.send_opcode(spi::opcodes::SETETHRST)?;
+        delay.delay_us(25);
        // Verify that EUDAST is 0x0000
        eudast = self.spi_port.read_reg_16b(spi::addrs::EUDAST)?;
        if eudast != 0x0000 {
-            return Err(EthControllerError::GeneralError)
+            return Err(Error::RegisterError);
        }
-        // Wait for 256us
-        delay.delay_us(256_u16);
+        delay.delay_us(256);
        Ok(())
    }

-    fn init_rxbuf(&mut self) -> Result<(), EthControllerError> {
+    pub fn init_rxbuf(&mut self) -> Result<(), Error> {
        // Set ERXST pointer
-        self.spi_port.write_reg_16b(spi::addrs::ERXST, self.rx_buf.get_wrap_addr())?;
+        self.spi_port
+            .write_reg_16b(spi::addrs::ERXST, self.rx_buf.get_start_addr())?;
        // Set ERXTAIL pointer
-        self.spi_port.write_reg_16b(spi::addrs::ERXTAIL, self.rx_buf.get_tail_addr())?;
+        self.spi_port
+            .write_reg_16b(spi::addrs::ERXTAIL, self.rx_buf.get_tail_addr())?;
        // Set MAMXFL to maximum number of bytes in each accepted packet
-        self.spi_port.write_reg_16b(spi::addrs::MAMXFL, RAW_FRAME_LENGTH_MAX as u16)?;
-        // Enable RXEN (ECON1<0>)
-        let econ1 = self.spi_port.read_reg_16b(spi::addrs::ECON1)?;
-        self.spi_port.write_reg_16b(spi::addrs::ECON1, 0x1 | (econ1 & 0xfffe))?;
+        self.spi_port
+            .write_reg_16b(spi::addrs::MAMXFL, RAW_FRAME_LENGTH_MAX as u16)?;
+        // Enable RX - set RXEN (ECON1<0>) to 1
+        self.spi_port.send_opcode(spi::opcodes::ENABLERX)?;
        Ok(())
    }

-    fn init_txbuf(&mut self) -> Result<(), EthControllerError> {
+    pub fn init_txbuf(&mut self) -> Result<(), Error> {
        // Set EGPWRPT pointer
        self.spi_port.write_reg_16b(spi::addrs::EGPWRPT, 0x0000)?;
        Ok(())
    }

+    /// Set controller to Promiscuous Mode
+    pub fn set_promiscuous(&mut self) -> Result<(), Error> {
+        // From Section 10.12, ENC424J600 Data Sheet:
+        // "To accept all incoming frames regardless of content (Promiscuous mode),
+        // set the CRCEN, RUNTEN, UCEN, NOTMEEN and MCEN bits."
+        let erxfcon_lo = self.spi_port.read_reg_8b(spi::addrs::ERXFCON)?;
+        self.spi_port.write_reg_8b(
+            spi::addrs::ERXFCON,
+            0b0101_1110 | (erxfcon_lo & 0b1010_0001),
+        )?;
+        Ok(())
+    }
+
+    /// Read MAC to [u8; 6]
+    pub fn read_mac_addr(&mut self, mac: &mut [u8]) -> Result<(), Error> {
+        mac[0] = self.spi_port.read_reg_8b(spi::addrs::MAADR1)?;
+        mac[1] = self.spi_port.read_reg_8b(spi::addrs::MAADR1 + 1)?;
+        mac[2] = self.spi_port.read_reg_8b(spi::addrs::MAADR2)?;
+        mac[3] = self.spi_port.read_reg_8b(spi::addrs::MAADR2 + 1)?;
+        mac[4] = self.spi_port.read_reg_8b(spi::addrs::MAADR3)?;
+        mac[5] = self.spi_port.read_reg_8b(spi::addrs::MAADR3 + 1)?;
+        Ok(())
+    }
+
+    pub fn write_mac_addr(&mut self, mac: &[u8]) -> Result<(), Error> {
+        self.spi_port.write_reg_8b(spi::addrs::MAADR1, mac[0])?;
+        self.spi_port.write_reg_8b(spi::addrs::MAADR1 + 1, mac[1])?;
+        self.spi_port.write_reg_8b(spi::addrs::MAADR2, mac[2])?;
+        self.spi_port.write_reg_8b(spi::addrs::MAADR2 + 1, mac[3])?;
+        self.spi_port.write_reg_8b(spi::addrs::MAADR3, mac[4])?;
+        self.spi_port.write_reg_8b(spi::addrs::MAADR3 + 1, mac[5])?;
+        Ok(())
+    }
+}
+
+impl<SPI: Transfer<u8>, NSS: OutputPin> EthPhy for Enc424j600<SPI, NSS> {
    /// Receive the next packet and return it
    /// Set is_poll to true for returning until PKTIF is set;
    /// Set is_poll to false for returning Err when PKTIF is not set
-    fn receive_next(&mut self, is_poll: bool) -> Result<rx::RxPacket, EthControllerError> {
+    fn recv_packet(&mut self, is_poll: bool) -> Result<rx::RxPacket, Error> {
        // Poll PKTIF (EIR<4>) to check if it is set
        loop {
            let eir = self.spi_port.read_reg_16b(spi::addrs::EIR)?;
-            if eir & 0x40 == 0x40 { break }
+            if eir & 0x40 == 0x40 {
+                break;
+            }
            if !is_poll {
-                return Err(EthControllerError::NoRxPacketError)
+                return Err(Error::NoRxPacketError);
            }
        }
        // Set ERXRDPT pointer to next_addr
-        self.spi_port.write_reg_16b(spi::addrs::ERXRDPT, self.rx_buf.get_next_addr())?;
+        self.spi_port
+            .write_reg_16b(spi::addrs::ERXRDPT, self.rx_buf.get_next_addr())?;
        // Read 2 bytes to update next_addr
        let mut next_addr_buf = [0; 3];
        self.spi_port.read_rxdat(&mut next_addr_buf, 2)?;
-        self.rx_buf.set_next_addr((next_addr_buf[1] as u16) | ((next_addr_buf[2] as u16) << 8));
+        self.rx_buf
+            .set_next_addr((next_addr_buf[1] as u16) | ((next_addr_buf[2] as u16) << 8));
        // Read 6 bytes to update rsv
        let mut rsv_buf = [0; 7];
        self.spi_port.read_rxdat(&mut rsv_buf, 6)?;
@ -139,68 +182,61 @@ impl <SPI: Transfer<u8>,
        rx_packet.update_frame_length();
        // Read frame bytes
        let mut frame_buf = [0; RAW_FRAME_LENGTH_MAX];
-        self.spi_port.read_rxdat(&mut frame_buf, rx_packet.get_frame_length())?;
+        self.spi_port
+            .read_rxdat(&mut frame_buf, rx_packet.get_frame_length())?;
        rx_packet.copy_frame_from(&frame_buf[1..]);
        // Set ERXTAIL pointer to (next_addr - 2)
-        if self.rx_buf.get_next_addr() > rx::ERXST_DEFAULT {
-            self.spi_port.write_reg_16b(spi::addrs::ERXTAIL, self.rx_buf.get_next_addr() - 2)?;
+        // * Assume head, tail, next and wrap addresses are word-aligned (even)
+        // - If next_addr is at least (start_addr+2), then set tail pointer to the word right before next_addr
+        if self.rx_buf.get_next_addr() > self.rx_buf.get_start_addr() {
+            self.spi_port
+                .write_reg_16b(spi::addrs::ERXTAIL, self.rx_buf.get_next_addr() - 2)?;
+        // - Otherwise, next_addr will wrap, so set tail pointer to the last word address of RX buffer
        } else {
-            self.spi_port.write_reg_16b(spi::addrs::ERXTAIL, rx::RX_MAX_ADDRESS - 1)?;
+            self.spi_port
+                .write_reg_16b(spi::addrs::ERXTAIL, rx::RX_MAX_ADDRESS - 1)?;
        }
-        // Set PKTDEC (ECON1<88>) to decrement PKTCNT
-        let econ1_hi = self.spi_port.read_reg_8b(spi::addrs::ECON1 + 1)?;
-        self.spi_port.write_reg_8b(spi::addrs::ECON1 + 1, 0x01 | (econ1_hi & 0xfe))?;
+        // Decrement PKTCNT - set PKTDEC (ECON1<8>)
+        self.spi_port.send_opcode(spi::opcodes::SETPKTDEC)?;
        // Return the RxPacket
        Ok(rx_packet)
    }

    /// Send an established packet
-    fn send_raw_packet(&mut self, packet: &tx::TxPacket) -> Result<(), EthControllerError> {
+    fn send_packet(&mut self, packet: &tx::TxPacket) -> Result<(), Error> {
        // Set EGPWRPT pointer to next_addr
-        self.spi_port.write_reg_16b(spi::addrs::EGPWRPT, self.tx_buf.get_next_addr())?;
+        self.spi_port
+            .write_reg_16b(spi::addrs::EGPWRPT, self.tx_buf.get_next_addr())?;
        // Copy packet data to SRAM Buffer
        // 1-byte Opcode is included
        let mut txdat_buf: [u8; RAW_FRAME_LENGTH_MAX + 1] = [0; RAW_FRAME_LENGTH_MAX + 1];
        packet.write_frame_to(&mut txdat_buf[1..]);
-        self.spi_port.write_txdat(&mut txdat_buf, packet.get_frame_length())?;
+        self.spi_port
+            .write_txdat(&mut txdat_buf, packet.get_frame_length())?;
        // Set ETXST to packet start address
-        self.spi_port.write_reg_16b(spi::addrs::ETXST, self.tx_buf.get_next_addr())?;
+        self.spi_port
+            .write_reg_16b(spi::addrs::ETXST, self.tx_buf.get_next_addr())?;
        // Set ETXLEN to packet length
-        self.spi_port.write_reg_16b(spi::addrs::ETXLEN, packet.get_frame_length() as u16)?;
-        // Set TXRTS (ECON1<1>) to start transmission
-        let mut econ1_lo = self.spi_port.read_reg_8b(spi::addrs::ECON1)?;
-        self.spi_port.write_reg_8b(spi::addrs::ECON1, 0x02 | (econ1_lo & 0xfd))?;
+        self.spi_port
+            .write_reg_16b(spi::addrs::ETXLEN, packet.get_frame_length() as u16)?;
+        // Send packet - set TXRTS (ECON1<1>) to start transmission
+        self.spi_port.send_opcode(spi::opcodes::SETTXRTS)?;
        // Poll TXRTS (ECON1<1>) to check if it is reset
        loop {
-            econ1_lo = self.spi_port.read_reg_8b(spi::addrs::ECON1)?;
-            if econ1_lo & 0x02 == 0 { break }
+            let econ1_lo = self.spi_port.read_reg_8b(spi::addrs::ECON1)?;
+            if econ1_lo & 0x02 == 0 {
+                break;
+            }
        }
        // TODO: Read ETXSTAT to understand Ethernet transmission status
        // (See: Register 9-2, ENC424J600 Data Sheet)
        // Update TX buffer start address
-        self.tx_buf.set_next_addr((self.tx_buf.get_next_addr() + packet.get_frame_length() as u16) %
-            tx::GPBUFEN_DEFAULT);
-        Ok(())
-    }
-
-    /// Set controller to Promiscuous Mode
-    fn set_promiscuous(&mut self) -> Result<(), EthControllerError> {
-        // From Section 10.12, ENC424J600 Data Sheet:
-        // "To accept all incoming frames regardless of content (Promiscuous mode),
-        // set the CRCEN, RUNTEN, UCEN, NOTMEEN and MCEN bits."
-        let erxfcon_lo = self.spi_port.read_reg_8b(spi::addrs::ERXFCON)?;
-        self.spi_port.write_reg_8b(spi::addrs::ERXFCON, 0b0101_1110 | (erxfcon_lo & 0b1010_0001))?;
-        Ok(())
-    }
-
-    /// Read MAC to [u8; 6]
-    fn read_from_mac(&mut self, mac: &mut [u8]) -> Result<(), EthControllerError> {
-        mac[0] = self.spi_port.read_reg_8b(spi::addrs::MAADR1)?;
-        mac[1] = self.spi_port.read_reg_8b(spi::addrs::MAADR1 + 1)?;
-        mac[2] = self.spi_port.read_reg_8b(spi::addrs::MAADR2)?;
-        mac[3] = self.spi_port.read_reg_8b(spi::addrs::MAADR2 + 1)?;
-        mac[4] = self.spi_port.read_reg_8b(spi::addrs::MAADR3)?;
-        mac[5] = self.spi_port.read_reg_8b(spi::addrs::MAADR3 + 1)?;
+        // * Assume TX buffer consumes the entire general-purpose SRAM block
+        self.tx_buf.set_next_addr(
+            (self.tx_buf.get_next_addr() + packet.get_frame_length() as u16)
+                % self.rx_buf.get_start_addr()
+                - self.tx_buf.get_start_addr(),
+        );
        Ok(())
    }
 }
--- a/src/rx.rs
+++ b/src/rx.rs
@ -11,38 +11,38 @@ pub const RSV_LENGTH: usize = 6;
 /// Struct for RX Buffer on the hardware
 /// TODO: Should be a singleton
 pub struct RxBuffer {
-    wrap_addr: u16,
+    start_addr: u16,
    next_addr: u16,
-    tail_addr: u16
+    tail_addr: u16,
 }

 impl RxBuffer {
    pub fn new() -> Self {
        RxBuffer {
-            wrap_addr: ERXST_DEFAULT,
+            start_addr: ERXST_DEFAULT,
            next_addr: ERXST_DEFAULT,
-            tail_addr: ERXTAIL_DEFAULT
+            tail_addr: ERXTAIL_DEFAULT,
        }
    }

-    pub fn set_wrap_addr(&mut self, addr: u16) {
-        self.wrap_addr = addr;
+    pub fn set_start_addr(&mut self, addr: u16) {
+        self.start_addr = addr;
    }
-    pub fn get_wrap_addr(& self) -> u16{
-        self.wrap_addr
+    pub fn get_start_addr(&self) -> u16 {
+        self.start_addr
    }

    pub fn set_next_addr(&mut self, addr: u16) {
        self.next_addr = addr;
    }
-    pub fn get_next_addr(& self) -> u16{
+    pub fn get_next_addr(&self) -> u16 {
        self.next_addr
    }

    pub fn set_tail_addr(&mut self, addr: u16) {
        self.tail_addr = addr;
    }
-    pub fn get_tail_addr(& self) -> u16{
+    pub fn get_tail_addr(&self) -> u16 {
        self.tail_addr
    }
 }
@ -52,7 +52,7 @@ impl RxBuffer {
 pub struct RxPacket {
    rsv: Rsv,
    frame: [u8; RAW_FRAME_LENGTH_MAX],
-    frame_length: usize
+    frame_length: usize,
 }

 impl RxPacket {
@ -60,7 +60,7 @@ impl RxPacket {
        RxPacket {
            rsv: Rsv::new(),
            frame: [0; RAW_FRAME_LENGTH_MAX],
-            frame_length: 0
+            frame_length: 0,
        }
    }

@ -106,14 +106,14 @@ impl RxPacket {
 struct Rsv {
    raw_rsv: [u8; RSV_LENGTH],
    // TODO: Add more definitions
-    frame_length: u16
+    frame_length: u16,
 }

 impl Rsv {
    fn new() -> Self {
        Rsv {
            raw_rsv: [0; RSV_LENGTH],
-            frame_length: 0_u16
+            frame_length: 0_u16,
        }
    }

@ -132,4 +132,4 @@ impl Rsv {
    fn get_frame_length(&self) -> u16 {
        self.frame_length
    }
-}
+}
--- a/src/smoltcp_phy.rs
+++ b/src/smoltcp_phy.rs
@ -1,32 +1,30 @@
-use crate::{
-    EthController, tx, RAW_FRAME_LENGTH_MAX
-};
+use crate::{tx, EthPhy, RAW_FRAME_LENGTH_MAX};
 use core::cell;
 use smoltcp::{
    phy::{Device, DeviceCapabilities, RxToken, TxToken},
    time::Instant,
-    Error
+    Error,
 };

-pub struct SmoltcpDevice<EC: EthController> {
-    pub eth_controller: cell::RefCell<EC>,
+pub struct SmoltcpDevice<E: EthPhy> {
+    pub eth_phy: cell::RefCell<E>,
    rx_packet_buf: [u8; RAW_FRAME_LENGTH_MAX],
-    tx_packet_buf: [u8; RAW_FRAME_LENGTH_MAX]
+    tx_packet_buf: [u8; RAW_FRAME_LENGTH_MAX],
 }

-impl<EC: EthController> SmoltcpDevice<EC> {
-    pub fn new(eth_controller: EC) -> Self {
+impl<E: EthPhy> SmoltcpDevice<E> {
+    pub fn new(eth_phy: E) -> Self {
        SmoltcpDevice {
-            eth_controller: cell::RefCell::new(eth_controller),
+            eth_phy: cell::RefCell::new(eth_phy),
            rx_packet_buf: [0; RAW_FRAME_LENGTH_MAX],
-            tx_packet_buf: [0; RAW_FRAME_LENGTH_MAX]
+            tx_packet_buf: [0; RAW_FRAME_LENGTH_MAX],
        }
    }
 }

-impl<'a, EC: 'a + EthController> Device<'a> for SmoltcpDevice<EC> {
+impl<'a, E: 'a + EthPhy> Device<'a> for SmoltcpDevice<E> {
    type RxToken = EthRxToken<'a>;
-    type TxToken = EthTxToken<'a, EC>;
+    type TxToken = EthTxToken<'a, E>;

    fn capabilities(&self) -> DeviceCapabilities {
        let mut caps = DeviceCapabilities::default();
@ -35,33 +33,33 @@ impl<'a, EC: 'a + EthController> Device<'a> for SmoltcpDevice<EC> {
    }

    fn receive(&'a mut self) -> Option<(Self::RxToken, Self::TxToken)> {
-        let self_p = (&mut *self) as *mut SmoltcpDevice<EC>;
-        match self.eth_controller.borrow_mut().receive_next(false) {
+        let self_p = (&mut *self) as *mut SmoltcpDevice<E>;
+        match self.eth_phy.borrow_mut().recv_packet(false) {
            Ok(rx_packet) => {
                // Write received packet to RX packet buffer
                rx_packet.write_frame_to(&mut self.rx_packet_buf);
                // Construct a RxToken
                let rx_token = EthRxToken {
                    buf: &mut self.rx_packet_buf,
-                    len: rx_packet.get_frame_length()
+                    len: rx_packet.get_frame_length(),
                };
                // Construct a blank TxToken
                let tx_token = EthTxToken {
                    buf: &mut self.tx_packet_buf,
-                    dev: self_p
+                    dev: self_p,
                };
                Some((rx_token, tx_token))
-            },
-            Err(_) => None
+            }
+            Err(_) => None,
        }
    }

    fn transmit(&'a mut self) -> Option<Self::TxToken> {
-        let self_p = (&mut *self) as *mut SmoltcpDevice<EC>;
+        let self_p = (&mut *self) as *mut SmoltcpDevice<E>;
        // Construct a blank TxToken
        let tx_token = EthTxToken {
            buf: &mut self.tx_packet_buf,
-            dev: self_p
+            dev: self_p,
        };
        Some(tx_token)
    }
@ -69,7 +67,7 @@ impl<'a, EC: 'a + EthController> Device<'a> for SmoltcpDevice<EC> {

 pub struct EthRxToken<'a> {
    buf: &'a mut [u8],
-    len: usize
+    len: usize,
 }

 impl<'a> RxToken for EthRxToken<'a> {
@ -81,12 +79,12 @@ impl<'a> RxToken for EthRxToken<'a> {
    }
 }

-pub struct EthTxToken<'a, EC: EthController> {
+pub struct EthTxToken<'a, E: EthPhy> {
    buf: &'a mut [u8],
-    dev: *mut SmoltcpDevice<EC>
+    dev: *mut SmoltcpDevice<E>,
 }

-impl<'a, EC: 'a + EthController> TxToken for EthTxToken<'a, EC> {
+impl<'a, E: 'a + EthPhy> TxToken for EthTxToken<'a, E> {
    fn consume<R, F>(self, _timestamp: Instant, len: usize, f: F) -> Result<R, Error>
    where
        F: FnOnce(&mut [u8]) -> Result<R, Error>,
@ -97,12 +95,10 @@ impl<'a, EC: 'a + EthController> TxToken for EthTxToken<'a, EC> {
        // Update frame length and write frame bytes
        tx_packet.update_frame(&mut self.buf[..len], len);
        // Send the packet as raw
-        let eth_controller = unsafe {
-            &mut (*self.dev).eth_controller
-        };
-        match eth_controller.borrow_mut().send_raw_packet(&tx_packet) {
-            Ok(_) => { result },
-            Err(_) => Err(Error::Exhausted)
+        let eth_phy = unsafe { &mut (*self.dev).eth_phy };
+        match eth_phy.borrow_mut().send_packet(&tx_packet) {
+            Ok(_) => result,
+            Err(_) => Err(Error::Exhausted),
        }
    }
 }
--- a/src/spi.rs
+++ b/src/spi.rs
@ -1,7 +1,4 @@
-use embedded_hal::{
-    blocking::spi::Transfer,
-    digital::v2::OutputPin,
-};
+use embedded_hal::{blocking::spi::Transfer, digital::v2::OutputPin};

 pub mod interfaces {
    use embedded_hal::spi;
@ -15,181 +12,206 @@ pub mod interfaces {
 }

 pub mod opcodes {
-    /// SPI Opcodes
+    /// 1-byte Instructions
+    pub const SETETHRST: u8 = 0b1100_1010;
+    pub const SETPKTDEC: u8 = 0b1100_1100;
+    pub const SETTXRTS: u8 = 0b1101_0100;
+    pub const ENABLERX: u8 = 0b1110_1000;
+    /// 3-byte Instructions
+    pub const WRXRDPT: u8 = 0b0110_0100; // 8-bit opcode followed by data
+    pub const RRXRDPT: u8 = 0b0110_0110; // 8-bit opcode followed by data
+    pub const WGPWRPT: u8 = 0b0110_1100; // 8-bit opcode followed by data
+    pub const RGPWRPT: u8 = 0b0110_1110; // 8-bit opcode followed by data
+    /// N-byte Instructions
    pub const RCRU: u8 = 0b0010_0000;
    pub const WCRU: u8 = 0b0010_0010;
-    pub const RERXDATA: u8 = 0b0010_1100;   // 8-bit opcode followed by data
-    pub const WEGPDATA: u8 = 0b0010_1010;   // 8-bit opcode followed by data
+    pub const RRXDATA: u8 = 0b0010_1100; // 8-bit opcode followed by data
+    pub const WGPDATA: u8 = 0b0010_1010; // 8-bit opcode followed by data
 }

 pub mod addrs {
    /// SPI Register Mapping
    /// Note: PSP interface use different address mapping
    // SPI Init Reset Registers
-    pub const EUDAST: u8 = 0x16;        // 16-bit data
-    pub const ESTAT: u8 = 0x1a;         // 16-bit data
-    pub const ECON2: u8 = 0x6e;         // 16-bit data
-    //
-    pub const ERXFCON: u8 = 0x34;       // 16-bit data
-    //
-    pub const MAADR3: u8 = 0x60;        // 16-bit data
-    pub const MAADR2: u8 = 0x62;        // 16-bit data
-    pub const MAADR1: u8 = 0x64;        // 16-bit data
-    // RX Registers
-    pub const ERXRDPT: u8 = 0x8a;       // 16-bit data
-    pub const ERXST: u8 = 0x04;         // 16-bit data
-    pub const ERXTAIL: u8 = 0x06;       // 16-bit data
-    pub const EIR: u8 = 0x1c;           // 16-bit data
-    pub const ECON1: u8 = 0x1e;         // 16-bit data
-    pub const MAMXFL: u8 = 0x4a;        // 16-bit data
-    // TX Registers
-    pub const EGPWRPT: u8 = 0x88;       // 16-bit data
-    pub const ETXST: u8 = 0x00;         // 16-bit data
-    pub const ETXSTAT: u8 = 0x12;       // 16-bit data
-    pub const ETXLEN: u8 = 0x02;        // 16-bit data
+    pub const EUDAST: u8 = 0x16; // 16-bit data
+    pub const ESTAT: u8 = 0x1a; // 16-bit data
+    pub const ECON2: u8 = 0x6e; // 16-bit data
+                                //
+    pub const ERXFCON: u8 = 0x34; // 16-bit data
+                                  //
+    pub const MAADR3: u8 = 0x60; // 16-bit data
+    pub const MAADR2: u8 = 0x62; // 16-bit data
+    pub const MAADR1: u8 = 0x64; // 16-bit data
+                                 // RX Registers
+    pub const ERXRDPT: u8 = 0x8a; // 16-bit data
+    pub const ERXST: u8 = 0x04; // 16-bit data
+    pub const ERXTAIL: u8 = 0x06; // 16-bit data
+    pub const EIR: u8 = 0x1c; // 16-bit data
+    pub const ECON1: u8 = 0x1e; // 16-bit data
+    pub const MAMXFL: u8 = 0x4a; // 16-bit data
+                                 // TX Registers
+    pub const EGPWRPT: u8 = 0x88; // 16-bit data
+    pub const ETXST: u8 = 0x00; // 16-bit data
+    pub const ETXSTAT: u8 = 0x12; // 16-bit data
+    pub const ETXLEN: u8 = 0x02; // 16-bit data
 }

 /// Struct for SPI I/O interface on ENC424J600
 /// Note: stm32f4xx_hal::spi's pins include: SCK, MISO, MOSI
-pub struct SpiPort<SPI: Transfer<u8>,
-                   NSS: OutputPin> {
+pub struct SpiPort<SPI: Transfer<u8>, NSS: OutputPin> {
    spi: SPI,
    nss: NSS,
+    #[cfg(feature = "cortex-m-cpu")]
+    cpu_freq_mhz: f32,
 }

-pub enum SpiPortError {
-    TransferError
+pub enum Error {
+    OpcodeError,
+    TransferError,
 }

 #[allow(unused_must_use)]
-impl <SPI: Transfer<u8>,
-      NSS: OutputPin> SpiPort<SPI, NSS> {
+impl<SPI: Transfer<u8>, NSS: OutputPin> SpiPort<SPI, NSS> {
    // TODO: return as Result()
    pub fn new(spi: SPI, mut nss: NSS) -> Self {
        nss.set_high();

        SpiPort {
            spi,
-            nss
+            nss,
+            #[cfg(feature = "cortex-m-cpu")]
+            cpu_freq_mhz: 0.,
        }
    }

-    pub fn read_reg_8b(&mut self, addr: u8) -> Result<u8, SpiPortError> {
-        // Using RCRU instruction to read using unbanked (full) address
-        let r_data = self.rw_addr_u8(opcodes::RCRU, addr, 0)?;
-        Ok(r_data)
+    #[cfg(feature = "cortex-m-cpu")]
+    pub fn cpu_freq_mhz(mut self, freq: u32) -> Self {
+        self.cpu_freq_mhz = freq as f32;
+        self
    }

-    pub fn read_reg_16b(&mut self, lo_addr: u8) -> Result<u16, SpiPortError> {
-        let r_data_lo = self.read_reg_8b(lo_addr)?;
-        let r_data_hi = self.read_reg_8b(lo_addr + 1)?;
-        // Combine top and bottom 8-bit to return 16-bit
-        Ok(((r_data_hi as u16) << 8) | r_data_lo as u16)
+    pub fn read_reg_8b(&mut self, addr: u8) -> Result<u8, Error> {
+        // Using RCRU instruction to read using unbanked (full) address
+        let mut buf: [u8; 4] = [0; 4];
+        buf[1] = addr;
+        self.rw_n(&mut buf, opcodes::RCRU, 2)?;
+        Ok(buf[2])
+    }
+
+    pub fn read_reg_16b(&mut self, lo_addr: u8) -> Result<u16, Error> {
+        // Unless the register can be written with specific opcode,
+        // use WCRU instruction to write using unbanked (full) address
+        let mut buf: [u8; 4] = [0; 4];
+        let mut data_offset = 0; // number of bytes separating
+                                 // actual data from opcode
+        match lo_addr {
+            addrs::ERXRDPT | addrs::EGPWRPT => {}
+            _ => {
+                buf[1] = lo_addr;
+                data_offset = 1;
+            }
+        }
+        self.rw_n(
+            &mut buf,
+            match lo_addr {
+                addrs::ERXRDPT => opcodes::RRXRDPT,
+                addrs::EGPWRPT => opcodes::RGPWRPT,
+                _ => opcodes::RCRU,
+            },
+            2 + data_offset, // extra 8-bit lo_addr before data
+        )?;
+        Ok(buf[data_offset + 1] as u16 | (buf[data_offset + 2] as u16) << 8)
    }

    // Currently requires manual slicing (buf[1..]) for the data read back
-    pub fn read_rxdat<'a>(&mut self, buf: &'a mut [u8], data_length: usize)
-                         -> Result<(), SpiPortError> {
-        let r_valid = self.r_n(buf, opcodes::RERXDATA, data_length)?;
-        Ok(r_valid)
+    pub fn read_rxdat<'a>(&mut self, buf: &'a mut [u8], data_length: usize) -> Result<(), Error> {
+        self.rw_n(buf, opcodes::RRXDATA, data_length)
    }

-    // Currenly requires actual data to be stored in buf[1..] instead of buf[0..]
+    // Currently requires actual data to be stored in buf[1..] instead of buf[0..]
    // TODO: Maybe better naming?
-    pub fn write_txdat<'a>(&mut self, buf: &'a mut [u8], data_length: usize)
-                          -> Result<(), SpiPortError> {
-        let w_valid = self.w_n(buf, opcodes::WEGPDATA, data_length)?;
-        Ok(w_valid)
+    pub fn write_txdat<'a>(&mut self, buf: &'a mut [u8], data_length: usize) -> Result<(), Error> {
+        self.rw_n(buf, opcodes::WGPDATA, data_length)
    }

-    pub fn write_reg_8b(&mut self, addr: u8, data: u8) -> Result<(), SpiPortError> {
-        // TODO: addr should be separated from w_data
+    pub fn write_reg_8b(&mut self, addr: u8, data: u8) -> Result<(), Error> {
        // Using WCRU instruction to write using unbanked (full) address
-        self.rw_addr_u8(opcodes::WCRU, addr, data)?;
-        Ok(())
-    }
-
-    pub fn write_reg_16b(&mut self, lo_addr: u8, data: u16) -> Result<(), SpiPortError> {
-        self.write_reg_8b(lo_addr, (data & 0xff) as u8)?;
-        self.write_reg_8b(lo_addr + 1, ((data & 0xff00) >> 8) as u8)?;
-        Ok(())
-    }
-
-    // TODO: Generalise transfer functions
-    // TODO: (Make data read/write as reference to array)
-    // Currently requires 1-byte addr, read/write data is only 1-byte
-    fn rw_addr_u8(&mut self, opcode: u8, addr: u8, data: u8)
-                 -> Result<u8, SpiPortError> {
-        // Enable chip select
-        self.nss.set_low();
-        // Start writing to SLAVE
-        // TODO: don't just use 3 bytes
        let mut buf: [u8; 3] = [0; 3];
-        buf[0] = opcode;
        buf[1] = addr;
        buf[2] = data;
-        match self.spi.transfer(&mut buf) {
-            Ok(_) => {
-                // Disable chip select
-                self.nss.set_high();
-                Ok(buf[2])
-            },
-            // TODO: Maybe too naive?
-            Err(_) => {
-                // Disable chip select
-                self.nss.set_high();
-                Err(SpiPortError::TransferError)
+        self.rw_n(&mut buf, opcodes::WCRU, 2)
+    }
+
+    pub fn write_reg_16b(&mut self, lo_addr: u8, data: u16) -> Result<(), Error> {
+        // Unless the register can be written with specific opcode,
+        // use WCRU instruction to write using unbanked (full) address
+        let mut buf: [u8; 4] = [0; 4];
+        let mut data_offset = 0; // number of bytes separating
+                                 // actual data from opcode
+        match lo_addr {
+            addrs::ERXRDPT | addrs::EGPWRPT => {}
+            _ => {
+                buf[1] = lo_addr;
+                data_offset = 1;
            }
        }
+        buf[1 + data_offset] = data as u8;
+        buf[2 + data_offset] = (data >> 8) as u8;
+        self.rw_n(
+            &mut buf,
+            match lo_addr {
+                addrs::ERXRDPT => opcodes::WRXRDPT,
+                addrs::EGPWRPT => opcodes::WGPWRPT,
+                _ => opcodes::WCRU,
+            },
+            2 + data_offset, // extra 8-bit lo_addr before data
+        )
+    }
+
+    pub fn send_opcode(&mut self, opcode: u8) -> Result<(), Error> {
+        match opcode {
+            opcodes::SETETHRST | opcodes::SETPKTDEC | opcodes::SETTXRTS | opcodes::ENABLERX => {
+                let mut buf: [u8; 1] = [0];
+                self.rw_n(&mut buf, opcode, 0)
+            }
+            _ => Err(Error::OpcodeError),
+        }
    }

-    // TODO: Generalise transfer functions
-    // Currently does NOT accept addr, read data is N-byte long
-    // Returns a reference to the data returned
-    // Note: buf must be at least (data_length + 1)-byte long
-    // TODO: Check and raise error for array size < (data_length + 1)
-    fn r_n<'a>(&mut self, buf: &'a mut [u8], opcode: u8, data_length: usize)
-              -> Result<(), SpiPortError> {
-        // Enable chip select
-        self.nss.set_low();
-        // Start writing to SLAVE
-        buf[0] = opcode;
-        match self.spi.transfer(&mut buf[..data_length+1]) {
-            Ok(_) => {
-                // Disable chip select
-                self.nss.set_high();
-                Ok(())
-            },
-            // TODO: Maybe too naive?
-            Err(_) => {
-                // Disable chip select
-                self.nss.set_high();
-                Err(SpiPortError::TransferError)
-            }
-        }
-    }
-
-    // Note: buf[0] is currently reserved for opcode to overwrite
    // TODO: Actual data should start from buf[0], not buf[1]
-    fn w_n<'a>(&mut self, buf: &'a mut [u8], opcode: u8, data_length: usize)
-              -> Result<(), SpiPortError> {
+    // Completes an SPI transfer for reading data to the given buffer,
+    // or writing data from the buffer.
+    // It sends an 8-bit instruction, followed by either
+    // receiving or sending n*8-bit data.
+    // The slice of buffer provided must begin with the 8-bit instruction.
+    // If n = 0, the transfer will only involve sending the instruction.
+    fn rw_n<'a>(&mut self, buf: &'a mut [u8], opcode: u8, data_length: usize) -> Result<(), Error> {
+        assert!(buf.len() > data_length);
        // Enable chip select
        self.nss.set_low();
+        // >=50ns min. CS_n setup time
+        #[cfg(feature = "cortex-m-cpu")]
+        cortex_m::asm::delay((0.05 * (self.cpu_freq_mhz + 1.)) as u32);
        // Start writing to SLAVE
        buf[0] = opcode;
-        // TODO: Maybe need to copy data to buf later on
-        match self.spi.transfer(&mut buf[..data_length+1]) {
-            Ok(_) => {
+        let result = self.spi.transfer(&mut buf[..data_length + 1]);
+        match opcode {
+            opcodes::RCRU | opcodes::WCRU | opcodes::RRXDATA | opcodes::WGPDATA => {
                // Disable chip select
+                // >=50ns min. CS_n hold time
+                #[cfg(feature = "cortex-m-cpu")]
+                cortex_m::asm::delay((0.05 * (self.cpu_freq_mhz + 1.)) as u32);
                self.nss.set_high();
-                Ok(())
-            },
-            // TODO: Maybe too naive?
-            Err(_) => {
-                // Disable chip select
-                self.nss.set_high();
-                Err(SpiPortError::TransferError)
+                // >=20ns min. CS_n disable time
+                #[cfg(feature = "cortex-m-cpu")]
+                cortex_m::asm::delay((0.02 * (self.cpu_freq_mhz + 1.)) as u32);
            }
+            _ => {}
+        }
+        match result {
+            Ok(_) => Ok(()),
+            // TODO: Maybe too naive?
+            Err(_) => Err(Error::TransferError),
        }
    }
-}
+}
--- a/src/tx.rs
+++ b/src/tx.rs
@ -1,45 +1,41 @@
 use crate::RAW_FRAME_LENGTH_MAX;

-/// SRAM Addresses
-pub const GPBUFST_DEFAULT: u16 = 0x0000;    // Start of General-Purpose SRAM Buffer
-pub const GPBUFEN_DEFAULT: u16 = 0x5340;    // End of General-Purpose SRAM Buffer == ERXST default
-
 /// Struct for TX Buffer on the hardware
 /// TODO: Should be a singleton
 pub struct TxBuffer {
-    wrap_addr: u16,
+    start_addr: u16,
    // The following two fields are controlled by firmware
    next_addr: u16,
-    tail_addr: u16
+    tail_addr: u16,
 }

 impl TxBuffer {
    pub fn new() -> Self {
        TxBuffer {
-            wrap_addr: GPBUFST_DEFAULT,
-            next_addr: GPBUFST_DEFAULT + 1,
-            tail_addr: GPBUFST_DEFAULT
+            start_addr: 0x0000,
+            next_addr: 0x0001,
+            tail_addr: 0x0000,
        }
    }

-    pub fn set_wrap_addr(&mut self, addr: u16) {
-        self.wrap_addr = addr;
+    pub fn set_start_addr(&mut self, addr: u16) {
+        self.start_addr = addr;
    }
-    pub fn get_wrap_addr(& self) -> u16{
-        self.wrap_addr
+    pub fn get_start_addr(&self) -> u16 {
+        self.start_addr
    }

    pub fn set_next_addr(&mut self, addr: u16) {
        self.next_addr = addr;
    }
-    pub fn get_next_addr(& self) -> u16{
+    pub fn get_next_addr(&self) -> u16 {
        self.next_addr
    }

    pub fn set_tail_addr(&mut self, addr: u16) {
        self.tail_addr = addr;
    }
-    pub fn get_tail_addr(& self) -> u16{
+    pub fn get_tail_addr(&self) -> u16 {
        self.tail_addr
    }
 }
@ -48,14 +44,14 @@ impl TxBuffer {
 /// TODO: Generalise MAC addresses
 pub struct TxPacket {
    frame: [u8; RAW_FRAME_LENGTH_MAX],
-    frame_length: usize
+    frame_length: usize,
 }

 impl TxPacket {
    pub fn new() -> Self {
        TxPacket {
            frame: [0; RAW_FRAME_LENGTH_MAX],
-            frame_length: 0
+            frame_length: 0,
        }
    }
Author	SHA1	Message	Date
Ryan Summers	0ea7499543	Merge pull request #3 from quartiq/release/0.3.0 Prepping for release	2023-07-03 14:51:20 +02:00
Ryan Summers	237009b628	Reverting repo update	2023-07-03 14:48:02 +02:00
Ryan Summers	b1f98c3622	Prepping for release	2023-07-03 13:50:06 +02:00
Ryan Summers	753112e7b0	Merge pull request #1 from quartiq/feature/nal-removal Removing NAL, reordering dependencies	2023-07-03 13:45:28 +02:00
Ryan Summers	0ecfe84ea0	Fixing smoltcp features	2023-07-03 13:43:12 +02:00
Ryan Summers	207a75358f	Merge branch 'master' into feature/nal-removal	2023-07-03 13:39:50 +02:00
Ryan Summers	21ab601b0d	Merge pull request #2 from quartiq/feature/ci Adding CI, format	2023-07-03 13:37:12 +02:00
Ryan Summers	fc43e3b5c5	Fixing example features	2023-07-03 12:32:54 +02:00
Ryan Summers	e94d1df1ec	Adding dummy commit	2023-07-03 12:28:47 +02:00
Ryan Summers	0fa5c8f81c	Enabling features in examples	2023-07-03 12:27:35 +02:00
Ryan Summers	ed42d185df	Updating example features	2023-07-03 12:26:47 +02:00
Ryan Summers	253a1f6f1d	Adding format	2023-07-03 12:25:46 +02:00
Ryan Summers	273cf09ad2	Removing nal module	2023-07-03 12:23:44 +02:00
Ryan Summers	fb2fd17277	Removing NAL, reordering dependencies	2023-07-03 12:21:26 +02:00
Harry Ho	512fd154bd	nix: Use lib in place of deprecated stdenv.lib	2021-09-02 17:10:03 +08:00
Harry Ho	fbcc3778d2	spi: Always delay for NSS setup time * Fixes the lack of setup time delay of an fixed-byte command that immediately follows an N-byte command. * Extra 50ns will be inserted in-between fixed-byte commands but should be acceptable.	2021-06-23 12:49:21 +08:00
Harry Ho	bb6824b944	nal: Remove delay_ns func pointer	2021-06-04 13:21:02 +08:00
Harry Ho	d8b1132b8a	examples: Replace delay_ns with cortex-m delay	2021-06-03 15:06:24 +08:00
Harry Ho	999ca5f08a	spi: Replace delay_ns func pointer with delay on cortex-m * SPI NSS nanosecond delays now only takes place on Cortex-M CPUs	2021-06-03 15:03:43 +08:00
Harry Ho	9de8d77a24	Restore embedded_hal DelayUs for device init	2021-06-03 13:38:59 +08:00
Harry Ho	ec20970a50	spi: Impose stricter NSS timing	2021-06-03 12:03:35 +08:00
Harry Ho	35b7924431	spi: Add back NSS high delay conditionally based on opcode type	2021-06-03 11:51:09 +08:00
Harry Ho	d05d7f91e2	spi: Simplify all reg reads/writes as rw_n()	2021-06-03 11:51:09 +08:00
Harry Ho	27ba42c4fb	spi: Introduce certain 1 & 3-byte opcodes to replace reg read/writes	2021-06-03 11:51:09 +08:00
Harry Ho	edb1f64f26	nix: Use itm-tools from nixpkgs-21.05	2021-06-02 14:15:07 +08:00
Harry Ho	40a53cc0d6	spi: Fix Rx/Tx buffer logic & simplify * tx/rx: Rename wrap_addr to start_addr for clarity * Fix RX logic, when advancing the tail pointer, not retrieving the stored RX buffer start address but the default value instead * Fix TX logic, when advancing the head pointer for next transmission, not retrieving the stored TX buffer end address but the default value instead * Rename SPI-related const's to match the datasheet: RERXDATA→RRXDATA, WEGPDATA→WGPDATA * Remove useless const's for SRAM default addresses for TX buffer * Simplify code	2021-04-30 17:30:25 +08:00
Harry Ho	6d17703e6b	Add Enc424j600::init() for complete initialisation	2021-04-29 17:08:19 +08:00
Harry Ho	78e4d82660	examples: Simplify & fix naming	2021-04-29 17:08:18 +08:00
Harry Ho	b9b28f0725	Rename functions & classes for clarity * EthController → EthPhy * ::receive_next() → ::recv_packet() * ::send_raw_packet() → ::send_packet() * SpiEth -> Enc424j600 * ::read_from_mac() → ::read_mac_addr() * ::write_mac_address() → ::write_mac_addr() * EthControllerError → Error * ::GeneralError → ::RegisterError * spi::SpiPortError -> spi::Error	2021-04-29 17:07:28 +08:00
Harry Ho	3529fcd192	Turn EthController trait methods unrelated to PHY into instance methods	2021-04-29 17:03:51 +08:00
Harry Ho	232a08f110	nal: Fix comments & styling	2021-03-17 10:21:18 +08:00
Harry Ho	2eadb652ff	nal: Fix infinite loop when TX buffer is full * For example, if the PHY linkup is down, instead of looping until resumption of the linkup, a write operation now closes the socket for re-connection in the future	2021-03-16 10:25:23 +08:00
Harry Ho	6de19f43cc	nal: Prevent pushing duplicate handles for the same TcpSocket	2021-03-12 12:36:30 +08:00
Harry Ho	66c3aa534f	nal: socket (TcpSocket) → handle; internal_socket → socket	2021-03-12 11:26:07 +08:00
Harry Ho	99899e6657	nal: Fix read/write not pushing erroneous socket back to the stack * Based on quartiq's minimq as of `933687c2e4` * In minimq applications, a socket is expected to be returned when `nal::TcpStack::open()` is called * `MqttClient::read()`/`write()` takes away the TCP socket handle (wrapped as an `Option`) from its `RefCell`, and then calls `nal::TcpStack::read()`/`write()`; if NAL returns `nb::Error`, then the MQTT client will propagate and return the error, leaving `None` behind * Afterwards, when `MqttClient::socket_is_connected()` gets called (e.g. while polling the interface), it will detect that the socket handle is `None`, and attempt to call `nal::TcpStack::open()` * Since `open()` pops a socket from the array (`unused_handles`), when implementing this NAL the socket should have been pushed back to the stack, i.e. by `close()`; this prevents any future calls of `open()` from returning `NetworkError::NoSocket` due to emptiness of the array of socket handles	2021-03-11 17:32:44 +08:00
Harry Ho	d9e50bbcb6	nal: Prevent looping until the stack successfully connects to remote * `NetworkStack::connect()`: * Add timeout for connection attempt * Now returns the socket at TCP ESTABLISHED or CLOSED states, or after connection timeout * Split `NetworkStack::update()` into `update()` (for controlling the clock) and `poll()` (for polling the smoltcp EthernetInterface) * Also remove option `auto_time_update`; the main application is responsible for what values `embedded_time::clock::Clock::try_now()` should return	2021-03-05 14:52:57 +08:00
Harry Ho	6506562c3a	cargo: fix [package] meta	2021-01-28 17:56:14 +08:00
Harry Ho	3d471bff0a	cargo: cleanup features	2021-01-28 17:56:13 +08:00
occheung	b6d1b3828a	feature: add nal support	2021-01-26 17:21:53 +08:00
occheung	8da639b89d	cargo: bump smoltcp version	2021-01-26 15:41:16 +08:00
occheung	6021623813	lib: add write mac	2021-01-25 18:32:21 +08:00
occheung	1add94c12e	Remove cortex-m dependencies for delay (#2 ) Co-Authored-By: occheung <dc@m-labs.hk> Co-Committed-By: occheung <dc@m-labs.hk>	2021-01-25 12:35:23 +08:00
Sebastien Bourdeauducq	1ce193b8aa	add gitignore	2021-01-20 15:26:48 +08:00
Sebastien Bourdeauducq	04ca484ded	remove Cargo lockfile (this is a library)	2021-01-20 15:26:39 +08:00
Sebastien Bourdeauducq	01030f16a8	bump version	2021-01-20 15:22:24 +08:00
occheung	26dabd4dc0	spi: add CS delay	2021-01-18 15:33:27 +08:00
occheung	c4b62cc238	lib: derive debug for error for unwrapping	2021-01-18 15:33:03 +08:00
occheung	356c3aefe2	lib: reduce stack usage	2021-01-18 15:32:32 +08:00