Turn EthController trait methods unrelated to PHY into instance methods
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parent
232a08f110
commit
3529fcd192
83
src/lib.rs
83
src/lib.rs
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@ -20,15 +20,10 @@ pub mod nal;
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/// Max raw frame array size
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pub const RAW_FRAME_LENGTH_MAX: usize = 1518;
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/// Trait representing PHY layer of ENC424J600
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pub trait EthController {
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fn init_dev(&mut self) -> Result<(), EthControllerError>;
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fn init_rxbuf(&mut self) -> Result<(), EthControllerError>;
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fn init_txbuf(&mut self) -> Result<(), EthControllerError>;
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fn receive_next(&mut self, is_poll: bool) -> Result<rx::RxPacket, EthControllerError>;
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fn send_raw_packet(&mut self, packet: &tx::TxPacket) -> Result<(), EthControllerError>;
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fn set_promiscuous(&mut self) -> Result<(), EthControllerError>;
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fn read_from_mac(&mut self, mac: &mut [u8]) -> Result<(), EthControllerError>;
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fn write_mac_address(&mut self, mac: &[u8]) -> Result<(), EthControllerError>;
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}
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/// TODO: Improve these error types
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@ -65,12 +60,8 @@ impl <SPI: Transfer<u8>,
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tx_buf: tx::TxBuffer::new()
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}
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}
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}
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impl <SPI: Transfer<u8>,
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NSS: OutputPin,
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F: FnMut(u32) -> ()> EthController for SpiEth<SPI, NSS, F> {
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fn init_dev(&mut self) -> Result<(), EthControllerError> {
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pub fn init_dev(&mut self) -> Result<(), EthControllerError> {
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// Write 0x1234 to EUDAST
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self.spi_port.write_reg_16b(spi::addrs::EUDAST, 0x1234)?;
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// Verify that EUDAST is 0x1234
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@ -96,7 +87,7 @@ impl <SPI: Transfer<u8>,
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Ok(())
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}
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fn init_rxbuf(&mut self) -> Result<(), EthControllerError> {
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pub fn init_rxbuf(&mut self) -> Result<(), EthControllerError> {
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// Set ERXST pointer
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self.spi_port.write_reg_16b(spi::addrs::ERXST, self.rx_buf.get_wrap_addr())?;
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// Set ERXTAIL pointer
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@ -109,12 +100,47 @@ impl <SPI: Transfer<u8>,
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Ok(())
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}
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fn init_txbuf(&mut self) -> Result<(), EthControllerError> {
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pub fn init_txbuf(&mut self) -> Result<(), EthControllerError> {
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// Set EGPWRPT pointer
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self.spi_port.write_reg_16b(spi::addrs::EGPWRPT, 0x0000)?;
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Ok(())
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}
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/// Set controller to Promiscuous Mode
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pub fn set_promiscuous(&mut self) -> Result<(), EthControllerError> {
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// From Section 10.12, ENC424J600 Data Sheet:
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// "To accept all incoming frames regardless of content (Promiscuous mode),
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// set the CRCEN, RUNTEN, UCEN, NOTMEEN and MCEN bits."
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let erxfcon_lo = self.spi_port.read_reg_8b(spi::addrs::ERXFCON)?;
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self.spi_port.write_reg_8b(spi::addrs::ERXFCON, 0b0101_1110 | (erxfcon_lo & 0b1010_0001))?;
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Ok(())
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}
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/// Read MAC to [u8; 6]
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pub fn read_from_mac(&mut self, mac: &mut [u8]) -> Result<(), EthControllerError> {
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mac[0] = self.spi_port.read_reg_8b(spi::addrs::MAADR1)?;
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mac[1] = self.spi_port.read_reg_8b(spi::addrs::MAADR1 + 1)?;
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mac[2] = self.spi_port.read_reg_8b(spi::addrs::MAADR2)?;
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mac[3] = self.spi_port.read_reg_8b(spi::addrs::MAADR2 + 1)?;
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mac[4] = self.spi_port.read_reg_8b(spi::addrs::MAADR3)?;
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mac[5] = self.spi_port.read_reg_8b(spi::addrs::MAADR3 + 1)?;
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Ok(())
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}
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pub fn write_mac_address(&mut self, mac: &[u8]) -> Result<(), EthControllerError> {
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self.spi_port.write_reg_8b(spi::addrs::MAADR1, mac[0])?;
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self.spi_port.write_reg_8b(spi::addrs::MAADR1 + 1, mac[1])?;
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self.spi_port.write_reg_8b(spi::addrs::MAADR2, mac[2])?;
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self.spi_port.write_reg_8b(spi::addrs::MAADR2 + 1, mac[3])?;
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self.spi_port.write_reg_8b(spi::addrs::MAADR3, mac[4])?;
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self.spi_port.write_reg_8b(spi::addrs::MAADR3 + 1, mac[5])?;
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Ok(())
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}
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}
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impl <SPI: Transfer<u8>,
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NSS: OutputPin,
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F: FnMut(u32) -> ()> EthController for SpiEth<SPI, NSS, F> {
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/// Receive the next packet and return it
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/// Set is_poll to true for returning until PKTIF is set;
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/// Set is_poll to false for returning Err when PKTIF is not set
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@ -187,35 +213,4 @@ impl <SPI: Transfer<u8>,
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tx::GPBUFEN_DEFAULT);
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Ok(())
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}
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/// Set controller to Promiscuous Mode
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fn set_promiscuous(&mut self) -> Result<(), EthControllerError> {
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// From Section 10.12, ENC424J600 Data Sheet:
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// "To accept all incoming frames regardless of content (Promiscuous mode),
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// set the CRCEN, RUNTEN, UCEN, NOTMEEN and MCEN bits."
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let erxfcon_lo = self.spi_port.read_reg_8b(spi::addrs::ERXFCON)?;
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self.spi_port.write_reg_8b(spi::addrs::ERXFCON, 0b0101_1110 | (erxfcon_lo & 0b1010_0001))?;
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Ok(())
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}
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/// Read MAC to [u8; 6]
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fn read_from_mac(&mut self, mac: &mut [u8]) -> Result<(), EthControllerError> {
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mac[0] = self.spi_port.read_reg_8b(spi::addrs::MAADR1)?;
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mac[1] = self.spi_port.read_reg_8b(spi::addrs::MAADR1 + 1)?;
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mac[2] = self.spi_port.read_reg_8b(spi::addrs::MAADR2)?;
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mac[3] = self.spi_port.read_reg_8b(spi::addrs::MAADR2 + 1)?;
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mac[4] = self.spi_port.read_reg_8b(spi::addrs::MAADR3)?;
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mac[5] = self.spi_port.read_reg_8b(spi::addrs::MAADR3 + 1)?;
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Ok(())
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}
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fn write_mac_address(&mut self, mac: &[u8]) -> Result<(), EthControllerError> {
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self.spi_port.write_reg_8b(spi::addrs::MAADR1, mac[0])?;
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self.spi_port.write_reg_8b(spi::addrs::MAADR1 + 1, mac[1])?;
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self.spi_port.write_reg_8b(spi::addrs::MAADR2, mac[2])?;
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self.spi_port.write_reg_8b(spi::addrs::MAADR2 + 1, mac[3])?;
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self.spi_port.write_reg_8b(spi::addrs::MAADR3, mac[4])?;
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self.spi_port.write_reg_8b(spi::addrs::MAADR3 + 1, mac[5])?;
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Ok(())
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}
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}
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