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README.md

Stabilizer Firmware

Flow diagram

Hardware

Features

  • dual channel
  • SPI ADC
  • SPI DAC
  • 500 kHz rate, timed sampling
  • 2 µs latency, unmatched between channels
  • f32 IIR math
  • generic biquad (second order) IIR filter
  • anti-windup
  • derivative kick avoidance

Limitations/TODOs

  • Fixed AFE gains
  • The IP and MAC address are hardcoded
  • Expose configurable limits
  • 100Base-T only
  • Digital IO, GPIO header, AFE header, EEM header are not handled

Hardware

See https://github.com/sinara-hw/Stabilizer

Minimal bootstrapping documentation

  • Clone or download this
  • Get a recent openocd, a JTAG adapter ("st-link" or some clone) and everything connected and permissions setup. Most Nucleo boards have a detachable ST-Link v2 and are cheap.1
  • Get a multiarch gdb (or a cross arm gdb and edit .cargo/config accordingly)
  • Get rustup
  • rustup override add nightly
  • rustup target add thumbv7em-none-eabihf
  • openocd -f stabilizer.cfg and leave it running
  • cargo run --release

Protocol

Stabilizer can be configured via newline-delimited JSON over TCP. It listens on port 1235. stabilizer.py contains a reference implementation of the protocol.

  1. Build a cable: connect a standard 8 conductor ribbon with the wires numbered 1-8 to the pins on the St-Link v2 single row 2.54mm connector as 647513(82) ((i) marks an unused wire) and to the 1.27mm dual row on Stabilizer as 657483x2x1 (x marks an unused pin, enumeration is standard for dual row, as in the schematic). It's just folding the ribbon between wires 5 and 6. The signals on the ribbon are then NRST,TDI,TDO,TCK,TMS,3V3,GND,GND. ↩︎