Robert Jördens
efbf750b20
Merge remote-tracking branch 'origin/master' into rj/misc
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* origin/master:
Upgrade to serde-json-core v0.2.0
2021-02-15 08:55:40 +01:00
Robert Jördens
5fc45a659b
lockin-external: comment style [nfc]
2021-02-15 08:51:19 +01:00
Robert Jördens
b581a016ce
lockin: redundant new
2021-02-14 17:55:01 +01:00
4130292706
Upgrade to serde-json-core v0.2.0
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This also fixes the network interface for writing IIR coefficients.
2021-02-13 00:07:15 +00:00
Robert Jördens
a6d4099ed3
lowpass: expose natural gain, add bias
2021-02-12 11:06:59 +01:00
Robert Jördens
32b7058b47
lockin: 2nd order lowpass
2021-02-11 23:15:32 +01:00
Robert Jördens
b49f0a2eb9
complex: log2, update bins
2021-02-11 18:14:28 +01:00
Robert Jördens
3ae0b710bc
lowpass: reimplement better
2021-02-11 14:30:05 +01:00
Robert Jördens
30c2c2aac2
lowpass: i32, no multiplies
2021-02-10 11:39:19 +01:00
Robert Jördens
208ba8379a
dsp, lockin: use cascaded 1st order lowpasses
2021-02-09 20:37:46 +01:00
Ryan Summers
724768a72e
Adding safety docs
2021-02-09 14:37:49 +01:00
Ryan Summers
2e358dea26
Adding support for input capture prefilter configuration
2021-02-09 14:36:50 +01:00
Robert Jördens
611bd3e855
ad9959/pounder: tweaks
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* make a trait public
* use self-test
* this hasn't been tested
2021-02-08 15:24:52 +01:00
Robert Jördens
1b46f081c1
better formatting
2021-02-08 11:26:58 +01:00
Robert Jördens
deed11f110
lockin-external: simplify
2021-02-05 18:59:22 +01:00
Robert Jördens
0343e5d8ab
pounder timer is u16
2021-02-04 16:51:34 +01:00
Robert Jördens
f19988a1bd
up the sample rate
2021-02-04 15:42:45 +01:00
Robert Jördens
2d492055f3
pounder stamper: overflow at u32 boundary
2021-02-04 15:42:29 +01:00
Robert Jördens
8314844aeb
pounder: moved SAMPLE_BUFFER_SIZE
2021-02-04 13:36:24 +01:00
Robert Jördens
d32378e6c4
lockin-external: ignore timestamps related to capture overflows
2021-02-04 12:48:58 +01:00
Robert Jördens
f47ee38d31
move sample ticks and buffer size to design parameters
2021-02-04 12:48:25 +01:00
Robert Jördens
7ce90c4d31
input stamper: add deglitching
2021-02-04 12:47:35 +01:00
Robert Jördens
c557348523
core_intrinsics attr need to be in the lib crate
2021-02-03 15:26:13 +01:00
Robert Jördens
5945cfca75
Merge pull request #258 from vertigo-designs/feature/input-capture-fixes
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Updating input capture for timers
2021-02-03 14:54:55 +01:00
Ryan Summers
ef22f5ab92
Fixing pounder input capture source
2021-02-03 14:11:00 +01:00
Ryan Summers
4e6f65b3e0
Fixing spacing
2021-02-03 13:42:43 +01:00
Robert Jördens
672ddfa3c3
pounder: also adapt to new hal
2021-02-03 13:25:00 +01:00
Robert Jördens
c5fde8563c
deps: bump hal and smoltcp, adapt
2021-02-03 13:16:22 +01:00
Ryan Summers
b57b666473
Updating input capture for timers
2021-02-03 13:03:17 +01:00
Robert Jördens
e423eff0e2
lockin-external: add doc
2021-02-02 15:50:31 +01:00
Robert Jördens
bd71136cdf
hw/config: add TODO on synchronization
2021-02-02 15:46:50 +01:00
Robert Jördens
145b48074e
timers: remove spurious tim2 reset
2021-02-02 15:42:51 +01:00
Robert Jördens
ddbfa9d988
timestamping: docs and naming
2021-02-02 14:34:48 +01:00
Robert Jördens
e1c87c149f
timestamping_timer: also reset counter
2021-02-02 13:25:45 +01:00
Robert Jördens
854ed29b1a
timestamp: pass overflows to the top and ignore them there
2021-02-02 12:34:20 +01:00
Robert Jördens
4475a2d040
timestamping: full u32 range
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The sampling timer and the timestamping timer have the same period.
The sampling interval and the batch size are powers of two.
If the timestamping timer wraps at a power of two larger than the
batch period, it will wrap in sync with the batch period.
Even if it didn't the RPLL would handle that. But it requires that the
timer wraps at the u32/i32 boundary (or be shifted left to wrap there).
2021-02-02 11:36:10 +01:00
Robert Jördens
2144af5bcd
configuration: update to HITL ips
2021-02-01 19:32:20 +01:00
Robert Jördens
24a4486847
lockin-internal: rotate samples
2021-02-01 19:31:57 +01:00
Robert Jördens
9ee60824d4
lockin-internal: align processing with lockin-external
2021-02-01 18:15:51 +01:00
Robert Jördens
f9b5d29450
lockin: de-nest processing flow
2021-02-01 18:14:09 +01:00
Robert Jördens
b6e22b576b
iir: add const fn new()
2021-02-01 17:18:10 +01:00
Robert Jördens
656e3253ab
lockin-internal: document, streamline sequence
2021-02-01 17:09:06 +01:00
Robert Jördens
65a3f839a0
lockin: remove feed()
2021-02-01 13:42:38 +01:00
Robert Jördens
2c60103696
dsp: accu: add, iir: rename IIRState to Vec5
2021-02-01 12:23:47 +01:00
Robert Jördens
46a7d67027
lockin-internal: rename, adapt
2021-01-31 19:26:11 +01:00
Robert Jördens
6e1444f070
Merge pull request #247 from quartiq/dsp-iir-benches
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Dsp iir benches
2021-01-31 19:24:56 +01:00
Robert Jördens
8dc811da11
Merge pull request #240 from vertigo-designs/feature/lockin-app-refactor
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Adding internal lock-in integration demo
2021-01-31 19:14:08 +01:00
Robert Jördens
47089c267c
dsp: align iir and iir_int, add iir micro benches
2021-01-31 19:12:24 +01:00
Robert Jördens
80055076b8
lockin: scale output
2021-01-31 17:41:20 +01:00
Robert Jördens
82c8fa1a07
rpll: extend tests
2021-01-31 17:10:03 +01:00
Robert Jördens
David Nadlinger
Ryan Summers