pounder_test/src/bin/lockin.rs

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#![deny(warnings)]
#![no_std]
#![no_main]
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use core::sync::atomic::{fence, Ordering};
use miniconf::Miniconf;
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use serde::Deserialize;
use dsp::{Accu, Complex, ComplexExt, Lockin, RPLL};
use stabilizer::{
flatten_closures,
hardware::{
design_parameters, hal, setup, Adc0Input, Adc1Input, AdcCode, AfeGain,
Dac0Output, Dac1Output, DacCode, DigitalInput0, DigitalInput1,
InputPin, InputStamper, SystemTimer, AFE0, AFE1,
},
net::{NetworkState, NetworkUsers, Telemetry, TelemetryBuffer},
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};
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// A constant sinusoid to send on the DAC output.
// Full-scale gives a +/- 10.24V amplitude waveform. Scale it down to give +/- 1V.
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const ONE: i16 = ((1.0 / 10.24) * i16::MAX as f32) as _;
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const SQRT2: i16 = (ONE as f32 * 0.707) as _;
const DAC_SEQUENCE: [i16; design_parameters::SAMPLE_BUFFER_SIZE] =
[ONE, SQRT2, 0, -SQRT2, -ONE, -SQRT2, 0, SQRT2];
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#[derive(Copy, Clone, Debug, Deserialize, Miniconf)]
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enum Conf {
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Magnitude,
Phase,
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ReferenceFrequency,
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LogPower,
InPhase,
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Quadrature,
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Modulation,
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}
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#[derive(Copy, Clone, Debug, Miniconf, Deserialize, PartialEq)]
enum LockinMode {
Internal,
External,
}
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#[derive(Copy, Clone, Debug, Deserialize, Miniconf)]
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pub struct Settings {
afe: [AfeGain; 2],
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lockin_mode: LockinMode,
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pll_tc: [u8; 2],
lockin_tc: u8,
lockin_harmonic: i32,
lockin_phase: i32,
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output_conf: [Conf; 2],
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telemetry_period: u16,
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}
impl Default for Settings {
fn default() -> Self {
Self {
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afe: [AfeGain::G1; 2],
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lockin_mode: LockinMode::External,
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pll_tc: [21, 21], // frequency and phase settling time (log2 counter cycles)
lockin_tc: 6, // lockin lowpass time constant
lockin_harmonic: -1, // Harmonic index of the LO: -1 to _de_modulate the fundamental (complex conjugate)
lockin_phase: 0, // Demodulation LO phase offset
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output_conf: [Conf::InPhase, Conf::Quadrature],
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// The default telemetry period in seconds.
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telemetry_period: 10,
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}
}
}
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#[rtic::app(device = stabilizer::hardware::hal::stm32, peripherals = true, monotonic = stabilizer::hardware::SystemTimer)]
const APP: () = {
struct Resources {
afes: (AFE0, AFE1),
adcs: (Adc0Input, Adc1Input),
dacs: (Dac0Output, Dac1Output),
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network: NetworkUsers<Settings, Telemetry>,
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settings: Settings,
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telemetry: TelemetryBuffer,
digital_inputs: (DigitalInput0, DigitalInput1),
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timestamper: InputStamper,
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pll: RPLL,
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lockin: Lockin<4>,
}
#[init(spawn=[settings_update, telemetry])]
fn init(c: init::Context) -> init::LateResources {
// Configure the microcontroller
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let (mut stabilizer, _pounder) = setup(c.core, c.device);
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let network = NetworkUsers::new(
stabilizer.net.stack,
stabilizer.net.phy,
stabilizer.cycle_counter,
env!("CARGO_BIN_NAME"),
stabilizer.net.mac_address,
);
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let settings = Settings::default();
let pll = RPLL::new(
design_parameters::ADC_SAMPLE_TICKS_LOG2
+ design_parameters::SAMPLE_BUFFER_SIZE_LOG2,
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);
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// Spawn a settings and telemetry update for default settings.
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c.spawn.settings_update().unwrap();
c.spawn.telemetry().unwrap();
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// Enable ADC/DAC events
stabilizer.adcs.0.start();
stabilizer.adcs.1.start();
stabilizer.dacs.0.start();
stabilizer.dacs.1.start();
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// Start recording digital input timestamps.
stabilizer.timestamp_timer.start();
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// Start sampling ADCs.
stabilizer.adc_dac_timer.start();
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// Enable the timestamper.
stabilizer.timestamper.start();
init::LateResources {
afes: stabilizer.afes,
adcs: stabilizer.adcs,
dacs: stabilizer.dacs,
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network,
digital_inputs: stabilizer.digital_inputs,
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timestamper: stabilizer.timestamper,
telemetry: TelemetryBuffer::default(),
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settings,
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pll,
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lockin: Lockin::default(),
}
}
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/// Main DSP processing routine.
///
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/// See `dual-iir` for general notes on processing time and timing.
///
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/// This is an implementation of a externally (DI0) referenced PLL lockin on the ADC0 signal.
/// It outputs either I/Q or power/phase on DAC0/DAC1. Data is normalized to full scale.
/// PLL bandwidth, filter bandwidth, slope, and x/y or power/phase post-filters are available.
#[task(binds=DMA1_STR4, resources=[adcs, dacs, lockin, timestamper, pll, settings, telemetry], priority=2)]
#[inline(never)]
#[link_section = ".itcm.process"]
fn process(mut c: process::Context) {
let process::Resources {
adcs: (ref mut adc0, ref mut adc1),
dacs: (ref mut dac0, ref mut dac1),
ref settings,
ref mut telemetry,
ref mut lockin,
ref mut pll,
ref mut timestamper,
} = c.resources;
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let (reference_phase, reference_frequency) = match settings.lockin_mode
{
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LockinMode::External => {
let timestamp = timestamper.latest_timestamp().unwrap_or(None); // Ignore data from timer capture overflows.
let (pll_phase, pll_frequency) = pll.update(
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timestamp.map(|t| t as i32),
settings.pll_tc[0],
settings.pll_tc[1],
);
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(
pll_phase,
(pll_frequency
>> design_parameters::SAMPLE_BUFFER_SIZE_LOG2)
as i32,
)
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}
LockinMode::Internal => {
// Reference phase and frequency are known.
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(
1i32 << 30,
1i32 << (32 - design_parameters::SAMPLE_BUFFER_SIZE_LOG2),
)
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}
};
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let sample_frequency =
reference_frequency.wrapping_mul(settings.lockin_harmonic);
let sample_phase = settings.lockin_phase.wrapping_add(
reference_phase.wrapping_mul(settings.lockin_harmonic),
);
flatten_closures!(with_buffer, adc0, adc1, dac0, dac1, {
let adc_samples = [adc0, adc1];
let mut dac_samples = [dac0, dac1];
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// Preserve instruction and data ordering w.r.t. DMA flag access.
fence(Ordering::SeqCst);
let output: Complex<i32> = adc_samples[0]
.iter()
// Zip in the LO phase.
.zip(Accu::new(sample_phase, sample_frequency))
// Convert to signed, MSB align the ADC sample, update the Lockin (demodulate, filter)
.map(|(&sample, phase)| {
let s = (sample as i16 as i32) << 16;
lockin.update(s, phase, settings.lockin_tc)
})
// Decimate
.last()
.unwrap()
* 2; // Full scale assuming the 2f component is gone.
// Convert to DAC data.
for (channel, samples) in dac_samples.iter_mut().enumerate() {
for (i, sample) in samples.iter_mut().enumerate() {
let value = match settings.output_conf[channel] {
Conf::Magnitude => output.abs_sqr() as i32 >> 16,
Conf::Phase => output.arg() >> 16,
Conf::LogPower => (output.log2() << 24) as i32 >> 16,
Conf::ReferenceFrequency => {
reference_frequency as i32 >> 16
}
Conf::InPhase => output.re >> 16,
Conf::Quadrature => output.im >> 16,
Conf::Modulation => DAC_SEQUENCE[i] as i32,
};
*sample = DacCode::from(value as i16).0;
}
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}
// Update telemetry measurements.
telemetry.adcs =
[AdcCode(adc_samples[0][0]), AdcCode(adc_samples[1][0])];
telemetry.dacs =
[DacCode(dac_samples[0][0]), DacCode(dac_samples[1][0])];
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// Preserve instruction and data ordering w.r.t. DMA flag access.
fence(Ordering::SeqCst);
});
}
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#[idle(resources=[network], spawn=[settings_update])]
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fn idle(mut c: idle::Context) -> ! {
loop {
match c.resources.network.lock(|net| net.update()) {
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NetworkState::SettingsChanged => {
c.spawn.settings_update().unwrap()
}
NetworkState::Updated => {}
NetworkState::NoChange => cortex_m::asm::wfi(),
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}
}
}
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#[task(priority = 1, resources=[network, settings, afes])]
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fn settings_update(mut c: settings_update::Context) {
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let settings = c.resources.network.miniconf.settings();
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c.resources.afes.0.set_gain(settings.afe[0]);
c.resources.afes.1.set_gain(settings.afe[1]);
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c.resources.settings.lock(|current| *current = *settings);
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}
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#[task(priority = 1, resources=[network, digital_inputs, settings, telemetry], schedule=[telemetry])]
fn telemetry(mut c: telemetry::Context) {
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let mut telemetry: TelemetryBuffer =
c.resources.telemetry.lock(|telemetry| *telemetry);
telemetry.digital_inputs = [
c.resources.digital_inputs.0.is_high().unwrap(),
c.resources.digital_inputs.1.is_high().unwrap(),
];
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let (gains, telemetry_period) = c
.resources
.settings
.lock(|settings| (settings.afe, settings.telemetry_period));
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c.resources
.network
.telemetry
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.publish(&telemetry.finalize(gains[0], gains[1]));
// Schedule the telemetry task in the future.
c.schedule
.telemetry(
c.scheduled
+ SystemTimer::ticks_from_secs(telemetry_period as u32),
)
.unwrap();
}
#[task(binds = ETH, priority = 1)]
fn eth(_: eth::Context) {
unsafe { hal::ethernet::interrupt_handler() }
}
#[task(binds = SPI2, priority = 3)]
fn spi2(_: spi2::Context) {
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panic!("ADC0 SPI error");
}
#[task(binds = SPI3, priority = 3)]
fn spi3(_: spi3::Context) {
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panic!("ADC1 SPI error");
}
#[task(binds = SPI4, priority = 3)]
fn spi4(_: spi4::Context) {
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panic!("DAC0 SPI error");
}
#[task(binds = SPI5, priority = 3)]
fn spi5(_: spi5::Context) {
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panic!("DAC1 SPI error");
}
extern "C" {
// hw interrupt handlers for RTIC to use for scheduling tasks
// one per priority
fn DCMI();
fn JPEG();
fn SDMMC();
}
};