2021-01-20 21:19:28 +08:00
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#![deny(warnings)]
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#![no_std]
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#![no_main]
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2021-06-01 20:49:51 +08:00
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use core::sync::atomic::{fence, Ordering};
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2021-06-04 17:59:54 +08:00
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use miniconf::Miniconf;
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2021-03-02 02:48:45 +08:00
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use serde::Deserialize;
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use dsp::{Accu, Complex, ComplexExt, Lockin, RPLL};
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2021-05-17 19:01:45 +08:00
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use stabilizer::{
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2021-06-04 17:59:54 +08:00
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flatten_closures,
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2021-05-17 19:01:45 +08:00
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hardware::{
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design_parameters, hal, setup, Adc0Input, Adc1Input, AdcCode, AfeGain,
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Dac0Output, Dac1Output, DacCode, DigitalInput0, DigitalInput1,
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InputPin, InputStamper, SystemTimer, AFE0, AFE1,
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},
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2021-06-04 17:59:54 +08:00
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net::{NetworkState, NetworkUsers, Telemetry, TelemetryBuffer},
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2021-01-20 21:29:29 +08:00
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};
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2021-03-02 02:48:45 +08:00
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2021-05-06 19:02:39 +08:00
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// A constant sinusoid to send on the DAC output.
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// Full-scale gives a +/- 10.24V amplitude waveform. Scale it down to give +/- 1V.
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2021-05-06 20:40:28 +08:00
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const ONE: i16 = ((1.0 / 10.24) * i16::MAX as f32) as _;
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2021-05-06 19:02:39 +08:00
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const SQRT2: i16 = (ONE as f32 * 0.707) as _;
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const DAC_SEQUENCE: [i16; design_parameters::SAMPLE_BUFFER_SIZE] =
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[ONE, SQRT2, 0, -SQRT2, -ONE, -SQRT2, 0, SQRT2];
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2021-03-03 00:29:20 +08:00
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#[derive(Copy, Clone, Debug, Deserialize, Miniconf)]
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2021-03-02 02:48:45 +08:00
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enum Conf {
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2021-05-06 20:40:28 +08:00
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Magnitude,
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Phase,
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2021-05-06 23:10:38 +08:00
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ReferenceFrequency,
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2021-05-06 20:40:28 +08:00
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LogPower,
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InPhase,
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2021-03-02 02:48:45 +08:00
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Quadrature,
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2021-05-06 20:40:28 +08:00
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Modulation,
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2021-03-02 02:48:45 +08:00
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}
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2021-05-06 19:02:39 +08:00
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#[derive(Copy, Clone, Debug, Miniconf, Deserialize, PartialEq)]
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enum LockinMode {
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Internal,
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External,
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}
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2021-03-03 00:29:20 +08:00
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#[derive(Copy, Clone, Debug, Deserialize, Miniconf)]
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2021-03-02 02:48:45 +08:00
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pub struct Settings {
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afe: [AfeGain; 2],
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2021-05-06 19:02:39 +08:00
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lockin_mode: LockinMode,
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2021-03-02 02:48:45 +08:00
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pll_tc: [u8; 2],
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lockin_tc: u8,
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lockin_harmonic: i32,
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lockin_phase: i32,
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2021-03-02 18:46:19 +08:00
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output_conf: [Conf; 2],
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2021-05-07 19:02:14 +08:00
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telemetry_period: u16,
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2021-03-02 02:48:45 +08:00
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}
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impl Default for Settings {
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fn default() -> Self {
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Self {
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2021-03-02 18:46:19 +08:00
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afe: [AfeGain::G1; 2],
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2021-03-02 02:48:45 +08:00
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2021-05-06 19:02:39 +08:00
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lockin_mode: LockinMode::External,
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2021-03-02 02:48:45 +08:00
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pll_tc: [21, 21], // frequency and phase settling time (log2 counter cycles)
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lockin_tc: 6, // lockin lowpass time constant
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lockin_harmonic: -1, // Harmonic index of the LO: -1 to _de_modulate the fundamental (complex conjugate)
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lockin_phase: 0, // Demodulation LO phase offset
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2021-05-06 20:40:28 +08:00
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output_conf: [Conf::InPhase, Conf::Quadrature],
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2021-05-10 17:10:26 +08:00
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// The default telemetry period in seconds.
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2021-05-07 19:02:14 +08:00
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telemetry_period: 10,
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2021-03-02 02:48:45 +08:00
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}
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}
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}
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2021-01-20 21:29:29 +08:00
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2021-05-17 19:01:45 +08:00
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#[rtic::app(device = stabilizer::hardware::hal::stm32, peripherals = true, monotonic = stabilizer::hardware::SystemTimer)]
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2021-01-20 21:19:28 +08:00
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const APP: () = {
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struct Resources {
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afes: (AFE0, AFE1),
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adcs: (Adc0Input, Adc1Input),
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dacs: (Dac0Output, Dac1Output),
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2021-05-05 22:16:54 +08:00
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network: NetworkUsers<Settings, Telemetry>,
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2021-03-02 02:48:45 +08:00
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settings: Settings,
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2021-05-05 22:16:54 +08:00
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telemetry: TelemetryBuffer,
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2021-04-20 20:12:47 +08:00
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digital_inputs: (DigitalInput0, DigitalInput1),
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2021-01-20 21:29:29 +08:00
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timestamper: InputStamper,
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2021-01-25 18:45:55 +08:00
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pll: RPLL,
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2021-05-10 23:31:53 +08:00
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lockin: Lockin<4>,
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2021-01-20 21:19:28 +08:00
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}
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2021-04-20 20:12:47 +08:00
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#[init(spawn=[settings_update, telemetry])]
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2021-01-20 21:19:28 +08:00
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fn init(c: init::Context) -> init::LateResources {
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// Configure the microcontroller
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2021-03-02 02:48:45 +08:00
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let (mut stabilizer, _pounder) = setup(c.core, c.device);
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2021-05-05 22:16:54 +08:00
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let network = NetworkUsers::new(
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stabilizer.net.stack,
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stabilizer.net.phy,
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stabilizer.cycle_counter,
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env!("CARGO_BIN_NAME"),
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stabilizer.net.mac_address,
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);
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2021-03-02 02:48:45 +08:00
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let settings = Settings::default();
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2021-01-20 21:19:28 +08:00
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2021-02-04 19:48:25 +08:00
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let pll = RPLL::new(
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design_parameters::ADC_SAMPLE_TICKS_LOG2
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+ design_parameters::SAMPLE_BUFFER_SIZE_LOG2,
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2021-01-21 21:55:33 +08:00
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);
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2021-01-20 21:29:29 +08:00
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2021-04-20 20:12:47 +08:00
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// Spawn a settings and telemetry update for default settings.
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2021-03-02 02:48:45 +08:00
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c.spawn.settings_update().unwrap();
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2021-04-20 20:12:47 +08:00
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c.spawn.telemetry().unwrap();
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2021-03-02 02:48:45 +08:00
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2021-01-20 21:19:28 +08:00
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// Enable ADC/DAC events
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stabilizer.adcs.0.start();
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stabilizer.adcs.1.start();
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stabilizer.dacs.0.start();
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stabilizer.dacs.1.start();
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2021-01-21 21:55:33 +08:00
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// Start recording digital input timestamps.
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stabilizer.timestamp_timer.start();
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2021-01-21 23:12:59 +08:00
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// Start sampling ADCs.
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stabilizer.adc_dac_timer.start();
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2021-02-03 20:03:17 +08:00
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// Enable the timestamper.
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stabilizer.timestamper.start();
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2021-01-20 21:19:28 +08:00
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init::LateResources {
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afes: stabilizer.afes,
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adcs: stabilizer.adcs,
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dacs: stabilizer.dacs,
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2021-05-05 21:39:33 +08:00
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network,
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2021-04-20 20:12:47 +08:00
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digital_inputs: stabilizer.digital_inputs,
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2021-01-20 21:29:29 +08:00
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timestamper: stabilizer.timestamper,
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2021-05-17 19:01:45 +08:00
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telemetry: TelemetryBuffer::default(),
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2021-03-02 02:48:45 +08:00
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settings,
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2021-02-18 00:22:43 +08:00
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2021-01-21 21:55:33 +08:00
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pll,
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2021-02-15 00:55:01 +08:00
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lockin: Lockin::default(),
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2021-01-20 21:19:28 +08:00
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}
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}
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2021-02-02 22:50:31 +08:00
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/// Main DSP processing routine.
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2021-01-20 21:19:28 +08:00
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///
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2021-02-02 22:50:31 +08:00
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/// See `dual-iir` for general notes on processing time and timing.
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2021-01-20 21:19:28 +08:00
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///
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2021-02-02 22:50:31 +08:00
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/// This is an implementation of a externally (DI0) referenced PLL lockin on the ADC0 signal.
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/// It outputs either I/Q or power/phase on DAC0/DAC1. Data is normalized to full scale.
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/// PLL bandwidth, filter bandwidth, slope, and x/y or power/phase post-filters are available.
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2021-04-20 20:12:47 +08:00
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#[task(binds=DMA1_STR4, resources=[adcs, dacs, lockin, timestamper, pll, settings, telemetry], priority=2)]
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2021-05-10 23:00:57 +08:00
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#[inline(never)]
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#[link_section = ".itcm.process"]
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2021-06-01 19:17:40 +08:00
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fn process(mut c: process::Context) {
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let process::Resources {
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adcs: (ref mut adc0, ref mut adc1),
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dacs: (ref mut dac0, ref mut dac1),
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ref settings,
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ref mut telemetry,
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ref mut lockin,
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ref mut pll,
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ref mut timestamper,
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} = c.resources;
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2021-01-20 21:19:28 +08:00
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2021-05-06 23:10:38 +08:00
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let (reference_phase, reference_frequency) = match settings.lockin_mode
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{
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2021-05-06 19:02:39 +08:00
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LockinMode::External => {
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2021-06-01 19:17:40 +08:00
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let timestamp = timestamper.latest_timestamp().unwrap_or(None); // Ignore data from timer capture overflows.
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let (pll_phase, pll_frequency) = pll.update(
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2021-05-06 19:02:39 +08:00
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timestamp.map(|t| t as i32),
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settings.pll_tc[0],
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settings.pll_tc[1],
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);
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2021-05-06 23:10:38 +08:00
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(
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pll_phase,
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(pll_frequency
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>> design_parameters::SAMPLE_BUFFER_SIZE_LOG2)
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as i32,
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)
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2021-05-06 19:02:39 +08:00
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}
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LockinMode::Internal => {
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// Reference phase and frequency are known.
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2021-05-06 23:10:38 +08:00
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(
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1i32 << 30,
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1i32 << (32 - design_parameters::SAMPLE_BUFFER_SIZE_LOG2),
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)
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2021-05-06 19:02:39 +08:00
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}
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};
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2021-01-20 21:19:28 +08:00
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2021-05-06 23:10:38 +08:00
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let sample_frequency =
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reference_frequency.wrapping_mul(settings.lockin_harmonic);
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let sample_phase = settings.lockin_phase.wrapping_add(
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reference_phase.wrapping_mul(settings.lockin_harmonic),
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);
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2021-06-01 19:17:40 +08:00
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flatten_closures!(with_buffer, adc0, adc1, dac0, dac1, {
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let adc_samples = [adc0, adc1];
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let mut dac_samples = [dac0, dac1];
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2021-06-01 20:49:51 +08:00
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// Preserve instruction and data ordering w.r.t. DMA flag access.
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fence(Ordering::SeqCst);
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2021-06-01 19:17:40 +08:00
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let output: Complex<i32> = adc_samples[0]
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.iter()
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// Zip in the LO phase.
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.zip(Accu::new(sample_phase, sample_frequency))
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// Convert to signed, MSB align the ADC sample, update the Lockin (demodulate, filter)
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.map(|(&sample, phase)| {
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let s = (sample as i16 as i32) << 16;
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lockin.update(s, phase, settings.lockin_tc)
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})
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// Decimate
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.last()
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.unwrap()
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* 2; // Full scale assuming the 2f component is gone.
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// Convert to DAC data.
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for (channel, samples) in dac_samples.iter_mut().enumerate() {
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for (i, sample) in samples.iter_mut().enumerate() {
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let value = match settings.output_conf[channel] {
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Conf::Magnitude => output.abs_sqr() as i32 >> 16,
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Conf::Phase => output.arg() >> 16,
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Conf::LogPower => (output.log2() << 24) as i32 >> 16,
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Conf::ReferenceFrequency => {
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reference_frequency as i32 >> 16
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}
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Conf::InPhase => output.re >> 16,
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Conf::Quadrature => output.im >> 16,
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Conf::Modulation => DAC_SEQUENCE[i] as i32,
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};
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*sample = DacCode::from(value as i16).0;
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}
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2021-05-06 19:02:39 +08:00
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}
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2021-06-01 19:17:40 +08:00
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// Update telemetry measurements.
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telemetry.adcs =
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[AdcCode(adc_samples[0][0]), AdcCode(adc_samples[1][0])];
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2021-04-20 20:12:47 +08:00
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2021-06-01 19:17:40 +08:00
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telemetry.dacs =
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[DacCode(dac_samples[0][0]), DacCode(dac_samples[1][0])];
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2021-04-20 20:12:47 +08:00
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2021-06-01 20:49:51 +08:00
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// Preserve instruction and data ordering w.r.t. DMA flag access.
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fence(Ordering::SeqCst);
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2021-06-01 19:17:40 +08:00
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});
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2021-01-20 21:19:28 +08:00
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}
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2021-05-05 21:39:33 +08:00
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#[idle(resources=[network], spawn=[settings_update])]
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2021-03-02 02:48:45 +08:00
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fn idle(mut c: idle::Context) -> ! {
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2021-01-20 21:19:28 +08:00
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loop {
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2021-05-05 22:46:53 +08:00
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match c.resources.network.lock(|net| net.update()) {
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2021-05-26 19:05:54 +08:00
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NetworkState::SettingsChanged => {
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c.spawn.settings_update().unwrap()
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}
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NetworkState::Updated => {}
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NetworkState::NoChange => cortex_m::asm::wfi(),
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2021-03-02 02:48:45 +08:00
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}
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2021-01-20 21:19:28 +08:00
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}
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}
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2021-05-05 21:39:33 +08:00
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#[task(priority = 1, resources=[network, settings, afes])]
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2021-03-02 02:48:45 +08:00
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fn settings_update(mut c: settings_update::Context) {
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2021-05-05 21:39:33 +08:00
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let settings = c.resources.network.miniconf.settings();
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2021-03-02 02:48:45 +08:00
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c.resources.afes.0.set_gain(settings.afe[0]);
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c.resources.afes.1.set_gain(settings.afe[1]);
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2021-05-04 19:13:44 +08:00
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c.resources.settings.lock(|current| *current = *settings);
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2021-03-02 02:48:45 +08:00
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}
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2021-05-05 21:39:33 +08:00
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#[task(priority = 1, resources=[network, digital_inputs, settings, telemetry], schedule=[telemetry])]
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2021-04-20 20:12:47 +08:00
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fn telemetry(mut c: telemetry::Context) {
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2021-05-06 22:23:41 +08:00
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let mut telemetry: TelemetryBuffer =
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c.resources.telemetry.lock(|telemetry| *telemetry);
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2021-04-20 20:12:47 +08:00
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telemetry.digital_inputs = [
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c.resources.digital_inputs.0.is_high().unwrap(),
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c.resources.digital_inputs.1.is_high().unwrap(),
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];
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2021-05-07 19:04:25 +08:00
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let (gains, telemetry_period) = c
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.resources
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.settings
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.lock(|settings| (settings.afe, settings.telemetry_period));
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2021-05-05 21:39:33 +08:00
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2021-05-05 22:16:54 +08:00
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c.resources
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.network
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.telemetry
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2021-05-06 18:33:07 +08:00
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.publish(&telemetry.finalize(gains[0], gains[1]));
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2021-04-20 20:12:47 +08:00
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// Schedule the telemetry task in the future.
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c.schedule
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.telemetry(
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c.scheduled
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+ SystemTimer::ticks_from_secs(telemetry_period as u32),
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)
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.unwrap();
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}
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|
2021-01-20 21:19:28 +08:00
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#[task(binds = ETH, priority = 1)]
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fn eth(_: eth::Context) {
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2021-05-17 19:01:45 +08:00
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unsafe { hal::ethernet::interrupt_handler() }
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2021-01-20 21:19:28 +08:00
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}
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#[task(binds = SPI2, priority = 3)]
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fn spi2(_: spi2::Context) {
|
2021-06-04 16:50:09 +08:00
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panic!("ADC0 SPI error");
|
2021-01-20 21:19:28 +08:00
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}
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#[task(binds = SPI3, priority = 3)]
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fn spi3(_: spi3::Context) {
|
2021-06-04 16:50:09 +08:00
|
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|
panic!("ADC1 SPI error");
|
2021-01-20 21:19:28 +08:00
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}
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#[task(binds = SPI4, priority = 3)]
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fn spi4(_: spi4::Context) {
|
2021-06-04 16:50:09 +08:00
|
|
|
panic!("DAC0 SPI error");
|
2021-01-20 21:19:28 +08:00
|
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}
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#[task(binds = SPI5, priority = 3)]
|
|
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|
fn spi5(_: spi5::Context) {
|
2021-06-04 16:50:09 +08:00
|
|
|
panic!("DAC1 SPI error");
|
2021-01-20 21:19:28 +08:00
|
|
|
}
|
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|
extern "C" {
|
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|
|
// hw interrupt handlers for RTIC to use for scheduling tasks
|
|
|
|
// one per priority
|
|
|
|
fn DCMI();
|
|
|
|
fn JPEG();
|
|
|
|
fn SDMMC();
|
|
|
|
}
|
|
|
|
};
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