327 lines
13 KiB
Rust
327 lines
13 KiB
Rust
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#![deny(warnings)]
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#![no_std]
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#![no_main]
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#![cfg_attr(feature = "nightly", feature(core_intrinsics))]
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use stm32h7xx_hal as hal;
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#[macro_use]
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extern crate log;
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use rtic::cyccnt::{Instant, U32Ext};
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use heapless::{consts::*, String};
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use stabilizer::{hardware, server};
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use dsp::iir;
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use hardware::{Adc0Input, Adc1Input, Dac0Output, Dac1Output, AFE0, AFE1};
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const SCALE: f32 = ((1 << 15) - 1) as f32;
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const TCP_RX_BUFFER_SIZE: usize = 8192;
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const TCP_TX_BUFFER_SIZE: usize = 8192;
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// The number of cascaded IIR biquads per channel. Select 1 or 2!
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const IIR_CASCADE_LENGTH: usize = 1;
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#[rtic::app(device = stm32h7xx_hal::stm32, peripherals = true, monotonic = rtic::cyccnt::CYCCNT)]
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const APP: () = {
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struct Resources {
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afes: (AFE0, AFE1),
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adcs: (Adc0Input, Adc1Input),
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dacs: (Dac0Output, Dac1Output),
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net_interface: hardware::Ethernet,
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// Format: iir_state[ch][cascade-no][coeff]
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#[init([[[0.; 5]; IIR_CASCADE_LENGTH]; 2])]
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iir_state: [[iir::IIRState; IIR_CASCADE_LENGTH]; 2],
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#[init([[iir::IIR { ba: [1., 0., 0., 0., 0.], y_offset: 0., y_min: -SCALE - 1., y_max: SCALE }; IIR_CASCADE_LENGTH]; 2])]
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iir_ch: [[iir::IIR; IIR_CASCADE_LENGTH]; 2],
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}
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#[init]
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fn init(c: init::Context) -> init::LateResources {
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// Configure the microcontroller
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let (mut stabilizer, _pounder) = hardware::setup(c.core, c.device);
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// Enable ADC/DAC events
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stabilizer.adcs.0.start();
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stabilizer.adcs.1.start();
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stabilizer.dacs.0.start();
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stabilizer.dacs.1.start();
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// Start sampling ADCs.
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stabilizer.adc_dac_timer.start();
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init::LateResources {
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afes: stabilizer.afes,
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adcs: stabilizer.adcs,
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dacs: stabilizer.dacs,
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net_interface: stabilizer.net.interface,
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}
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}
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/// Main DSP processing routine for Stabilizer.
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///
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/// # Note
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/// Processing time for the DSP application code is bounded by the following constraints:
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///
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/// DSP application code starts after the ADC has generated a batch of samples and must be
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/// completed by the time the next batch of ADC samples has been acquired (plus the FIFO buffer
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/// time). If this constraint is not met, firmware will panic due to an ADC input overrun.
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///
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/// The DSP application code must also fill out the next DAC output buffer in time such that the
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/// DAC can switch to it when it has completed the current buffer. If this constraint is not met
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/// it's possible that old DAC codes will be generated on the output and the output samples will
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/// be delayed by 1 batch.
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///
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/// Because the ADC and DAC operate at the same rate, these two constraints actually implement
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/// the same time bounds, meeting one also means the other is also met.
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#[task(binds=DMA1_STR4, resources=[adcs, dacs, iir_state, iir_ch], priority=2)]
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fn process(c: process::Context) {
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let adc_samples = [
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c.resources.adcs.0.acquire_buffer(),
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c.resources.adcs.1.acquire_buffer(),
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];
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let dac_samples = [
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c.resources.dacs.0.acquire_buffer(),
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c.resources.dacs.1.acquire_buffer(),
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];
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let iir_lockin = c.resources.iir_lockin;
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let iir_state_lockin = c.resources.iir_state_lockin;
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let iir_ch = c.resources.iir_ch;
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let iir_state = c.resources.iir_state;
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let (pll_phase, pll_frequency) = c
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.resources
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.timestamp_handler
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.update(c.resources.input_stamper.latest_timestamp());
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let frequency = pll_frequency.wrapping_mul(HARMONIC);
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let mut phase =
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PHASE_OFFSET.wrapping_add(pll_phase.wrapping_mul(HARMONIC));
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for i in 0..adc_samples[0].len() {
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let m = cossin((phase as i32).wrapping_neg());
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phase = phase.wrapping_add(frequency);
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let signal = Complex(
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iir_lockin.update(
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&mut iir_state_lockin[0],
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((adc_samples[0][i] as i64 * m.0 as i64) >> 16) as _,
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),
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iir_lockin.update(
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&mut iir_state_lockin[1],
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((adc_samples[0][i] as i64 * m.1 as i64) >> 16) as _,
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),
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);
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let mut magnitude =
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(signal.0 * signal.0 + signal.1 * signal.1) as _;
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let mut phase = atan2(signal.1, signal.0) as _;
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for j in 0..iir_state[0].len() {
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magnitude =
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iir_ch[0][j].update(&mut iir_state[0][j], magnitude);
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phase = iir_ch[1][j].update(&mut iir_state[1][j], phase);
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}
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// Note(unsafe): range clipping to i16 is ensured by IIR filters above.
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unsafe {
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dac_samples[0][i] =
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magnitude.to_int_unchecked::<i16>() as u16 ^ 0x8000;
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dac_samples[1][i] =
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phase.to_int_unchecked::<i16>() as u16 ^ 0x8000;
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}
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}
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}
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#[idle(resources=[net_interface, iir_state, iir_ch, afes])]
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fn idle(mut c: idle::Context) -> ! {
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let mut socket_set_entries: [_; 8] = Default::default();
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let mut sockets =
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smoltcp::socket::SocketSet::new(&mut socket_set_entries[..]);
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let mut rx_storage = [0; TCP_RX_BUFFER_SIZE];
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let mut tx_storage = [0; TCP_TX_BUFFER_SIZE];
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let tcp_handle = {
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let tcp_rx_buffer =
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smoltcp::socket::TcpSocketBuffer::new(&mut rx_storage[..]);
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let tcp_tx_buffer =
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smoltcp::socket::TcpSocketBuffer::new(&mut tx_storage[..]);
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let tcp_socket =
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smoltcp::socket::TcpSocket::new(tcp_rx_buffer, tcp_tx_buffer);
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sockets.add(tcp_socket)
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};
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let mut server = server::Server::new();
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let mut time = 0u32;
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let mut next_ms = Instant::now();
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// TODO: Replace with reference to CPU clock from CCDR.
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next_ms += 400_000.cycles();
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loop {
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let tick = Instant::now() > next_ms;
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if tick {
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next_ms += 400_000.cycles();
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time += 1;
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}
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{
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let socket =
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&mut *sockets.get::<smoltcp::socket::TcpSocket>(tcp_handle);
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if socket.state() == smoltcp::socket::TcpState::CloseWait {
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socket.close();
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} else if !(socket.is_open() || socket.is_listening()) {
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socket
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.listen(1235)
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.unwrap_or_else(|e| warn!("TCP listen error: {:?}", e));
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} else {
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server.poll(socket, |req| {
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info!("Got request: {:?}", req);
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stabilizer::route_request!(req,
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readable_attributes: [
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"stabilizer/iir/state": (|| {
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let state = c.resources.iir_state.lock(|iir_state|
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server::Status {
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t: time,
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x0: iir_state[0][0][0],
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y0: iir_state[0][0][2],
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x1: iir_state[1][0][0],
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y1: iir_state[1][0][2],
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});
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Ok::<server::Status, ()>(state)
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}),
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// "_b" means cascades 2nd IIR
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"stabilizer/iir_b/state": (|| { let state = c.resources.iir_state.lock(|iir_state|
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server::Status {
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t: time,
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x0: iir_state[0][IIR_CASCADE_LENGTH-1][0],
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y0: iir_state[0][IIR_CASCADE_LENGTH-1][2],
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x1: iir_state[1][IIR_CASCADE_LENGTH-1][0],
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y1: iir_state[1][IIR_CASCADE_LENGTH-1][2],
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});
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Ok::<server::Status, ()>(state)
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}),
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"stabilizer/afe0/gain": (|| c.resources.afes.0.get_gain()),
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"stabilizer/afe1/gain": (|| c.resources.afes.1.get_gain())
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],
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modifiable_attributes: [
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"stabilizer/iir0/state": server::IirRequest, (|req: server::IirRequest| {
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c.resources.iir_ch.lock(|iir_ch| {
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if req.channel > 1 {
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return Err(());
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}
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iir_ch[req.channel as usize][0] = req.iir;
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Ok::<server::IirRequest, ()>(req)
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})
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}),
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"stabilizer/iir1/state": server::IirRequest, (|req: server::IirRequest| {
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c.resources.iir_ch.lock(|iir_ch| {
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if req.channel > 1 {
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return Err(());
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}
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iir_ch[req.channel as usize][0] = req.iir;
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Ok::<server::IirRequest, ()>(req)
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})
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}),
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"stabilizer/iir_b0/state": server::IirRequest, (|req: server::IirRequest| {
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c.resources.iir_ch.lock(|iir_ch| {
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if req.channel > 1 {
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return Err(());
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}
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iir_ch[req.channel as usize][IIR_CASCADE_LENGTH-1] = req.iir;
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Ok::<server::IirRequest, ()>(req)
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})
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}),
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"stabilizer/iir_b1/state": server::IirRequest,(|req: server::IirRequest| {
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c.resources.iir_ch.lock(|iir_ch| {
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if req.channel > 1 {
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return Err(());
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}
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iir_ch[req.channel as usize][IIR_CASCADE_LENGTH-1] = req.iir;
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Ok::<server::IirRequest, ()>(req)
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})
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}),
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"stabilizer/afe0/gain": hardware::AfeGain, (|gain| {
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c.resources.afes.0.set_gain(gain);
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Ok::<(), ()>(())
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}),
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"stabilizer/afe1/gain": hardware::AfeGain, (|gain| {
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c.resources.afes.1.set_gain(gain);
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Ok::<(), ()>(())
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})
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]
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)
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});
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}
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}
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let sleep = match c.resources.net_interface.poll(
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&mut sockets,
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smoltcp::time::Instant::from_millis(time as i64),
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) {
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Ok(changed) => !changed,
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Err(smoltcp::Error::Unrecognized) => true,
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Err(e) => {
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info!("iface poll error: {:?}", e);
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true
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}
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};
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if sleep {
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cortex_m::asm::wfi();
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}
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}
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}
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#[task(binds = ETH, priority = 1)]
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fn eth(_: eth::Context) {
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unsafe { hal::ethernet::interrupt_handler() }
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}
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#[task(binds = SPI2, priority = 3)]
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fn spi2(_: spi2::Context) {
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panic!("ADC0 input overrun");
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}
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#[task(binds = SPI3, priority = 3)]
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fn spi3(_: spi3::Context) {
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panic!("ADC0 input overrun");
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}
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#[task(binds = SPI4, priority = 3)]
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fn spi4(_: spi4::Context) {
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panic!("DAC0 output error");
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}
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#[task(binds = SPI5, priority = 3)]
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fn spi5(_: spi5::Context) {
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panic!("DAC1 output error");
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}
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extern "C" {
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// hw interrupt handlers for RTIC to use for scheduling tasks
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// one per priority
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fn DCMI();
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fn JPEG();
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fn SDMMC();
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}
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};
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