dsleung
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  • Joined on 2020-05-28
Repositories Projects Packages Code Public Activity Starred Repositories
dsleung pushed to master at M-Labs/rtio-nmigen 2020-09-28 16:01:51 +08:00
7c742dc2d1 Add rtio.sed.lane_distributor
dsleung pushed to master at M-Labs/rtio-nmigen 2020-09-28 11:36:34 +08:00
bf08fe1d50 Add partial implementation of lane distributor
dsleung pushed to master at M-Labs/rtio-nmigen 2020-09-25 16:28:04 +08:00
49684c1990 Add partial implementation of CRI interface
dsleung pushed to master at M-Labs/rtio-nmigen 2020-09-25 15:10:15 +08:00
1a83778590 Remove redundant 'artiq.gateware' from module names
dsleung pushed to master at M-Labs/rtio-nmigen 2020-09-25 13:26:09 +08:00
a788c17e3d Add artiq.gateware.rtio.sed.layouts
dsleung pushed to master at M-Labs/rtio-nmigen 2020-09-25 12:59:37 +08:00
9e81676fd2 Add artiq.gateware.rtio.channel
dsleung pushed to master at M-Labs/rtio-nmigen 2020-09-25 12:49:22 +08:00
f7c1cc23a5 Implement artiq.gateware.rtio.rtlink
dsleung pushed to master at M-Labs/rtio-nmigen 2020-09-25 12:04:42 +08:00
0ec4604219 Add project structure
dsleung pushed to master at M-Labs/rtio-nmigen 2020-09-25 11:58:17 +08:00
7a08d78b6a Update README
dsleung pushed to master at M-Labs/rtio-nmigen 2020-09-25 11:45:41 +08:00
7a08d78b6a Update README
dsleung pushed to master at M-Labs/rtio-nmigen 2020-09-24 15:43:40 +08:00
2eb682ee3e Update README
dsleung pushed to master at M-Labs/rtio-nmigen 2020-09-24 15:11:31 +08:00
79aad630d2 Add shell.nix
dsleung pushed to master at M-Labs/rtio-nmigen 2020-09-23 17:17:04 +08:00
4046b4769d Update README.md
dsleung pushed to master at M-Labs/rtio-nmigen 2020-09-23 17:14:35 +08:00
0cc229e9d6 Add README and LICENSE
dsleung pushed to master at M-Labs/rtio-nmigen 2020-09-23 17:10:48 +08:00
130ef76d83 Add initial README
dsleung pushed to master at M-Labs/riscv-formal-nmigen 2020-09-21 13:45:43 +08:00
978a620cc6 Limit no. of parallel processes to prevent thrashing
dsleung pushed to master at M-Labs/riscv-formal-nmigen 2020-09-21 11:31:03 +08:00
c1a4617d74 Use m-labs nmigen repo
dsleung pushed to master at M-Labs/riscv-formal-nmigen 2020-09-18 16:00:07 +08:00
425bc49784 Parallelize all verification tasks for Minerva
dsleung pushed to master at M-Labs/riscv-formal-nmigen 2020-09-18 13:23:24 +08:00
b0a914b48e Parallelize instruction verification tasks
dsleung pushed to master at M-Labs/riscv-formal-nmigen 2020-09-17 17:07:05 +08:00
283d8531e0 Update README