Add project structure
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artiq/__init__.py
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artiq/__init__.py
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artiq/gateware/__init__.py
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artiq/gateware/__init__.py
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artiq/gateware/rtio/__init__.py
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artiq/gateware/rtio/__init__.py
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artiq/gateware/rtio/channel.py
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artiq/gateware/rtio/channel.py
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artiq/gateware/rtio/core.py
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artiq/gateware/rtio/core.py
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artiq/gateware/rtio/cri.py
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artiq/gateware/rtio/cri.py
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artiq/gateware/rtio/input_collector.py
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artiq/gateware/rtio/input_collector.py
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artiq/gateware/rtio/rtlink.py
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artiq/gateware/rtio/rtlink.py
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artiq/gateware/rtio/sed/__init__.py
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artiq/gateware/rtio/sed/__init__.py
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artiq/gateware/rtio/sed/core.py
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artiq/gateware/rtio/sed/core.py
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artiq/gateware/rtio/sed/fifos.py
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artiq/gateware/rtio/sed/fifos.py
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artiq/gateware/rtio/sed/gates.py
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artiq/gateware/rtio/sed/gates.py
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artiq/gateware/rtio/sed/lane_distributor.py
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artiq/gateware/rtio/sed/lane_distributor.py
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artiq/gateware/rtio/sed/layouts.py
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artiq/gateware/rtio/sed/layouts.py
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artiq/gateware/rtio/sed/output_driver.py
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artiq/gateware/rtio/sed/output_driver.py
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artiq/gateware/rtio/sed/output_network.py
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artiq/gateware/rtio/sed/output_network.py
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misoc/__init__.py
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misoc/__init__.py
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misoc/interconnect/__init__.py
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misoc/interconnect/__init__.py
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misoc/interconnect/csr.py
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misoc/interconnect/csr.py
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