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Donald Sebastian Leung 2020-09-24 15:43:33 +08:00
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README.md
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@ -5,6 +5,19 @@ Formally verified implementation of the ARTIQ RTIO core in nMigen
## Progress
- [ ] Implement the core in nMigen
- - [ ] `artiq.gateware.rtio.core`
- - [ ] `misoc.interconnect.csr`
- - [ ] `artiq.gateware.rtio.cri`
- - [ ] `artiq.gateware.rtio.rtlink`
- - [ ] `artiq.gateware.rtio.channel`
- - [ ] `artiq.gateware.rtio.sed.core`
- - [ ] `artiq.gateware.rtio.sed.layouts`
- - [ ] `artiq.gateware.rtio.sed.lane_distributor`
- - [ ] `artiq.gateware.rtio.sed.fifos`
- - [ ] `artiq.gateware.rtio.sed.gates`
- - [ ] `artiq.gateware.rtio.sed.output_driver`
- - [ ] `artiq.gateware.rtio.sed.output_network`
- - [ ] `artiq.gateware.rtio.input_collector`
- [ ] Add suitable assertions for verification (BMC / unbounded proof?)
## License