e1b2c45813
kasli_soc & zc706: Fix GTX Clock Path during INIT
2023-11-07 18:55:08 +08:00
e6372b9766
zynq_clocking: Allow ext signal to set cur_clk csr
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- for example, current_clock csr can be connected to tx_init.done
2023-11-07 18:55:08 +08:00
07044752b6
zynq_clocking: add ext_async_rst to AsyncRstSYNCR
2023-11-07 18:55:08 +08:00
79fc5a7789
zynq_clocking: expose mmcm_locked for SYSCRG
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- mmcm_locked -> self.mmcm_locked
2023-11-07 18:55:08 +08:00
b768d5648c
Add grabber module
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Signed-off-by: Egor Savkin <es@m-labs.hk>
2023-10-16 14:35:20 +08:00
136e24f597
kasli-soc: Add BUFG to the IBUFGDS for MMCM CLKIN1
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- Fix Vivado Compilation Error [DRC REQP-119]
- MMCME2_ADV CLKIN1 and CLKIN2 are now driven from the same source type (BUFG)
2023-10-11 16:45:26 +08:00
b15322b6ba
kasli_soc: Add support for shuttler on gateware
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- Port from artiq repo
- Add EEM_DRTIO gateware
2023-10-10 11:22:05 +08:00
8fd1306145
zynq_clocking: Add sys5x, 208MHz CLK & IDELAYCTRL
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- Port from artiq repo
- Generate sys5x for for EEM Serdes, 208MHz REF Clock for IDELAYCTRL
- Add IDELAYCTRL for IDEALYE2 in EEM Serdes
2023-10-10 11:21:34 +08:00
49205eea17
satellite gateware: add kernel rtio to cri
2023-10-09 11:36:23 +08:00
656cbf4546
kasli_soc: use sed_lanes value from HW description
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https://github.com/m-labs/artiq/pull/1745 added a field for setting the number of SED lanes to the HW description. This commit makes it so that the setting is used for Kasli Soc as well.
2023-10-06 15:37:56 +01:00
ae3099dd8e
kasli_soc: support 100MHz clock
2023-10-06 16:27:25 +08:00
b3856e879b
refactor write_rustc_cfg_file()
2023-09-11 11:48:19 +08:00
1ccae0d442
consolidate all write..file() into config.py
2023-09-11 11:48:19 +08:00
2c19f4ac31
replace rustc_cfg[ ] & change write_rustc_cfg_file
2023-09-11 11:48:19 +08:00
MorganTL
0e6309b95e
change write_rustc_cfg_file to follow artiq repo
2023-08-30 14:56:12 +08:00
622d267d55
add virtual LEDs, improve IO expander setup, drive TX_DISABLE
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Co-authored-by: morgan <mc@m-labs.hk>
Co-committed-by: morgan <mc@m-labs.hk>
2023-08-28 16:08:10 +08:00
4ae8557018
drtio: remame drtio_transceiver to gt_drtio
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Co-authored-by: linuswck <linuswck@m-labs.hk>
Co-committed-by: linuswck <linuswck@m-labs.hk>
2023-08-28 13:05:40 +08:00
ca17cd419e
Revert "kasli_soc: add SFP0..3 LED indication"
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This reverts commit 5111778363
2023-08-03 10:42:09 +08:00
5111778363
kasli_soc: add SFP0..3 LED indication
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Co-authored-by: morgan <mc@m-labs.hk>
Co-committed-by: morgan <mc@m-labs.hk>
2023-07-24 16:30:14 +08:00
ee438105b2
json: base -> drtio_role
2023-06-16 17:03:25 +08:00
63594d7e3d
update configuration of IBUFDS_GTE2
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Input clock is terminated internally with 50 Ohm on each leg and to 4/5 MGTAVCC.
2023-05-30 12:08:41 +08:00
ad076dd4e9
zc706: fix satellite analyzer target
2023-05-24 09:52:16 +08:00
c536a70890
satellite gateware: add rtio analyzer
2023-05-22 15:23:24 +08:00
b747abe83c
qc2: add 4 edge counters to the end of rtio
2023-04-03 12:25:07 +08:00
4b1ce1a6ff
satellites: add rtio_dma, connect as cri master
2023-03-21 15:54:58 +08:00
dce37a52aa
KasliSoC satellite: fix serdes timing
2023-02-20 13:07:42 +08:00
46b2687d70
RTIO/SYS Clock merge
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Co-authored-by: mwojcik <mw@m-labs.hk>
Co-committed-by: mwojcik <mw@m-labs.hk>
2023-02-17 15:52:43 +08:00
19e60073de
kasli_soc: ident = variant name
2022-10-21 11:55:24 +08:00
efc432352e
zc706: no syncrtio for master, fixes hangs ( #188 )
2022-05-03 14:36:10 +08:00
def4d989cd
kasli_soc: fix si5324 pins routed to GTX
2022-04-25 12:33:21 +08:00
1d731a3589
zc706 master: route sma clock to si5324
2022-04-13 16:35:52 +08:00
3cf86a6335
satellites: add rtio_crg cfg
2022-04-12 13:44:53 +08:00
a22b13cc46
kasli_soc: forward SMA clkin
2022-03-09 12:43:47 +08:00
85e5c08d7f
kasli_soc: use si5324 in master
2022-03-04 13:17:53 +08:00
31fb2b388a
Support for DRTIO 100MHz ( #155 )
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Co-authored-by: mwojcik <mw@m-labs.hk>
Co-committed-by: mwojcik <mw@m-labs.hk>
2021-12-03 17:19:42 +08:00
e045837b67
zc706: not actually ultrascale
2021-11-29 12:48:45 +08:00
ada3f2e704
drtio: reading still needs work buffer after all
2021-11-29 12:46:08 +08:00
8be5048cd3
upgrade to new clock configuration system ( #152 )
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As mentioned in https://github.com/m-labs/artiq/issues/1735 - this is the Zynq version.
Reviewed-on: M-Labs/artiq-zynq#152
Co-authored-by: mwojcik <mw@m-labs.hk>
Co-committed-by: mwojcik <mw@m-labs.hk>
2021-11-29 11:17:59 +08:00
0b27349ec4
dummy_spi -> pmod_spi
2021-10-14 16:37:13 +08:00
21eb1cab1a
zc706: added dummy spi in place of sdio
2021-10-14 15:43:51 +08:00
3096daaaee
zc706: removed nist_clock sdcard, put pmod instead
2021-10-14 15:01:38 +08:00
4fbfccf575
zc706: fix nist_qc2 extension, ams101 iostandard
2021-10-14 12:39:09 +08:00
5c40115945
make ZC706 RTIO channels consistent with KC705
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Reviewed-on: M-Labs/artiq-zynq#147
Co-authored-by: mwojcik <mw@m-labs.hk>
Co-committed-by: mwojcik <mw@m-labs.hk>
2021-10-13 17:20:25 +08:00
d04a7decfe
removed simple variants from zc706
2021-10-08 11:07:12 +02:00
4fa824f42b
kasli-soc: remove irrelevant comment
2021-10-08 16:13:17 +08:00
ab0c205dd2
gateware: add DRTIO
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Reviewed-on: M-Labs/artiq-zynq#140
Co-authored-by: mwojcik <mw@m-labs.hk>
Co-committed-by: mwojcik <mw@m-labs.hk>
2021-10-08 16:12:30 +08:00
18e05c91e1
zc706: si5324 is not needed for standalone target
2021-08-04 09:14:19 +08:00
e3d3cb2311
si5324: bring on par with mainline ARTIQ ( #132 )
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si5324 driver in runtime should be now equal in function to the one in artiq.
kasli-soc has no way of doing a hard reset on the peripheral, but zc706 does.
Reviewed-on: M-Labs/artiq-zynq#132
Co-authored-by: mwojcik <mw@m-labs.hk>
Co-committed-by: mwojcik <mw@m-labs.hk>
2021-08-04 09:12:38 +08:00
8128dc0b56
Revert "kasli-soc: work around I2C breakage ( #130 )"
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This reverts commit f1fd55dee5
2021-07-30 16:55:06 +08:00
852123b42a
kasli-soc: add RTIO LEDs
2021-05-30 20:40:53 +08:00
