forked from M-Labs/artiq-zynq
qc2: add 4 edge counters to the end of rtio
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@ -59,6 +59,14 @@ device_db["ad9914dds1"] = {
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"arguments": {"sysclk": 3e9, "bus_channel": 50, "channel": 1},
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}
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for i in range(4):
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device_db["ttl"+str(i)+"_counter"] = {
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"type": "local",
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"module": "artiq.coredevice.edge_counter",
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"class": "EdgeCounter",
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"arguments": {"channel": 52+i}
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}
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# for ARTIQ test suite
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device_db.update(
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loop_out="ttl0",
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@ -14,7 +14,7 @@ from misoc.integration import cpu_interface
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from misoc.cores import gpio
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from artiq.gateware import rtio, nist_clock, nist_qc2
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from artiq.gateware.rtio.phy import ttl_simple, ttl_serdes_7series, dds, spi2
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from artiq.gateware.rtio.phy import ttl_simple, ttl_serdes_7series, dds, spi2, edge_counter
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from artiq.gateware.rtio.xilinx_clocking import fix_serdes_timing_path
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from artiq.gateware.drtio.transceiver import gtx_7series
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from artiq.gateware.drtio.siphaser import SiPhaser7Series
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@ -577,12 +577,16 @@ class _NIST_QC2_RTIO:
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platform.add_extension(pmod1_33)
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rtio_channels = []
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edge_counter_phy = []
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# All TTL channels are In+Out capable
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for i in range(40):
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phy = ttl_serdes_7series.InOut_8X(platform.request("ttl", i))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512))
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# first four TTLs will also have edge counters
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if i < 4:
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edge_counter_phy.append(phy)
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# no SMA GPIO, replaced with PMOD1_0
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phy = ttl_serdes_7series.InOut_8X(platform.request("pmod1_33", 0))
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@ -621,6 +625,11 @@ class _NIST_QC2_RTIO:
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platform.request("dds", backplane_offset), 12, onehot=True)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4))
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for phy in edge_counter_phy:
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counter = edge_counter.SimpleEdgeCounter(phy.input_state)
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self.submodules += counter
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rtio_channels.append(rtio.Channel.from_phy(counter))
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self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
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rtio_channels.append(rtio.LogChannel())
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