cw/artiq-zynq
1
0
Fork 0
forked from M-Labs/artiq-zynq
Code Issues Pull Requests Releases Wiki Activity

satellite gateware: add kernel rtio to cri

Browse Source
This commit is contained in:
mwojcik 2023-09-05 16:12:03 +08:00
parent 6885c618b5
commit 49205eea17
2 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/gateware/kasli_soc.py
View File

@ -470,7 +470,7 @@ class GenericSatellite(SoCCore):
self.comb += self.drtiosat.async_errors.eq(self.local_io.async_errors)
self.submodules.cri_con = rtio.CRIInterconnectShared(
[self.drtiosat.cri, self.rtio_dma.cri],
[self.drtiosat.cri, self.rtio_dma.cri, self.rtio.cri],
[self.local_io.cri] + self.drtio_cri,
enable_routing=True)
self.csr_devices.append("cri_con")

2
src/gateware/zc706.py
View File

@ -476,7 +476,7 @@ class _SatelliteBase(SoCCore):
self.submodules.local_io = SyncRTIO(self.rtio_tsc, rtio_channels)
self.submodules.cri_con = rtio.CRIInterconnectShared(
[self.drtiosat.cri, self.rtio_dma.cri],
[self.drtiosat.cri, self.rtio_dma.cri, self.rtio.cri],
[self.local_io.cri] + self.drtio_cri,
enable_routing=True)
self.csr_devices.append("cri_con")