forked from M-Labs/artiq-zynq
satellite gateware: add kernel rtio to cri
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6885c618b5
commit
49205eea17
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@ -470,7 +470,7 @@ class GenericSatellite(SoCCore):
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self.comb += self.drtiosat.async_errors.eq(self.local_io.async_errors)
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self.submodules.cri_con = rtio.CRIInterconnectShared(
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[self.drtiosat.cri, self.rtio_dma.cri],
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[self.drtiosat.cri, self.rtio_dma.cri, self.rtio.cri],
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[self.local_io.cri] + self.drtio_cri,
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enable_routing=True)
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self.csr_devices.append("cri_con")
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@ -476,7 +476,7 @@ class _SatelliteBase(SoCCore):
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self.submodules.local_io = SyncRTIO(self.rtio_tsc, rtio_channels)
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self.submodules.cri_con = rtio.CRIInterconnectShared(
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[self.drtiosat.cri, self.rtio_dma.cri],
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[self.drtiosat.cri, self.rtio_dma.cri, self.rtio.cri],
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[self.local_io.cri] + self.drtio_cri,
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enable_routing=True)
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self.csr_devices.append("cri_con")
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