Commit Graph

607 Commits

Author SHA1 Message Date
b942cdcbc8 sdio: change Adma2Desc32 alignment from 1 to 4
this should not break anything.
2020-06-11 10:07:19 +08:00
a1a211334f eth: always just allocate desc list + buffers
buffers are allocated vec anyway. this removes the lifetime hack and
further prepares work on cache-line alignment to enable L1 writeback.
2020-06-11 00:21:18 +02:00
187ef703f2 experiments: use stream.close() instead of .flush() 2020-06-10 20:21:01 +02:00
cf17a1c60a removed unneeded methods 2020-06-10 12:55:22 +08:00
5332587de6 Changed mutability 2020-06-10 12:54:50 +08:00
0ebc4a61c8 Modified SDIO to handle u8 buffer instead of u32. 2020-06-09 17:03:17 +08:00
40d5eb8232 fixed compilation error 2020-06-05 12:27:41 +08:00
d01d0f69a4 formatting commit 2020-06-05 12:27:19 +08:00
236592ae66 SDIO module completed 2020-06-05 12:27:12 +08:00
a53ed8acc8 add remote run script 2020-06-04 19:57:52 +08:00
7695d6d8df openocd: fix cora z7-10 PL_TAPID 2020-05-16 01:34:09 +02:00
2c82fb793e Merge pull request 'sdio-registers' (#29) 2020-05-15 06:44:32 +08:00
0c48dd934e libboard_zynq: fix sclr::ddriob_ddr_ctrl vref_int_en 2020-05-10 22:14:55 +02:00
3841accd9c libboard_zynq: fix ddr memtest range 2020-05-09 02:53:58 +02:00
3e02980c20 libboard_zynq: fix access to "full" 1022 MB on target_zc706 2020-05-09 02:35:39 +02:00
66cd0c7630 libcortex_a9: allow access for full 1GB of DDR 2020-05-09 02:35:39 +02:00
4e1f46b3e2 core1: support redirecting vectors to sdram 2020-05-06 22:07:12 +08:00
pca
73b0ec9837 fixed typo 2020-05-06 13:58:46 +08:00
pca
4acee21c05 Merge branch 'master' of git.m-labs.hk:M-Labs/zc706 into sdio-registers 2020-05-06 11:06:38 +08:00
ce844f1b02 devc: add is_done() 2020-05-04 22:16:53 +08:00
60e996a121 update cargoSha256 2020-05-03 09:58:58 +08:00
27094da9ff nix: disable post-installation fixup on ARM binaries 2020-05-03 09:47:58 +08:00
c955eaae7f libboard_zynq: flush Uart by waiting for tx idle 2020-05-02 23:32:01 +02:00
0f666c570c libboard_zynq: remove unneeded Uart flush 2020-05-02 23:30:45 +02:00
pca
244ccdeac2 finished register definitions 2020-05-01 15:38:07 +08:00
e047c2900b ddr: log clock info with debug level 2020-05-01 12:27:43 +08:00
d86f69a253 Cargo.lock: cargo update 2020-05-01 01:53:39 +02:00
877f2c34bd libboard_zynq: use log logging 2020-05-01 01:46:42 +02:00
619ebf147c libsupport_zynq: move mod logger to libboard_zynq 2020-05-01 01:33:40 +02:00
6ab4869d05 experiments: disable flash_io tests, remove simple async experiments 2020-05-01 01:25:52 +02:00
172a8a6c45 experiments/link.x: assert at least 4 KB of stack 2020-05-01 01:25:25 +02:00
0d4d021b1b clean up 2020-05-01 01:17:53 +02:00
2c756ba32e libcortex_a9: migrate from asm! to llvm_asm! to avoid future breakage 2020-05-01 01:11:35 +02:00
008a995429 libcortex_a9: remove mmu::l1_table alignment through linker script
no longer needed, #[repr(16384)] works now
2020-04-30 03:38:27 +02:00
pca
d9e8a667bd some macro changes and more registers 2020-04-29 21:19:24 +08:00
pca
b22cc4e2b6 various control registers 2020-04-29 09:34:17 +08:00
pca
3238dae99f started writing register definitions 2020-04-28 23:00:47 +08:00
83ff37e10e link.x: cleanup 2020-04-28 19:39:35 +08:00
248a692cf7 link.x: fix indentation 2020-04-28 19:35:45 +08:00
3948021458 define core1 stack in linker script 2020-04-28 19:31:49 +08:00
1c270a55e2 move linker script to experiments
Not all applications are in OCM.
2020-04-28 19:14:03 +08:00
282b4dc69a link.x: reduce alignment, use all remaining OCM for .stack 2020-04-28 02:50:07 +02:00
b88e14ea07 move build.rs, link.x into libsupport_zynq/ 2020-04-28 01:51:58 +02:00
2802d21d08 libsupport_zynq: fix doc 2020-04-28 01:13:08 +02:00
614b1ef350 regs: add MVBAR and HVBAR 2020-04-27 12:49:18 +08:00
fefd2a4ceb regs: add VBAR 2020-04-27 12:34:15 +08:00
dfcdeb09ca alloc: support initializing from linker information 2020-04-27 10:06:55 +08:00
aa93794632 libboard_zynq: add GlobalTimer::get_us(), use in libsupport_zynq::logger 2020-04-25 03:01:19 +02:00
fe6a058a6b libboard_zynq: find prescaler for GlobalTimer, rename new() to start() 2020-04-25 02:59:48 +02:00
22555017fe default.nix: fix 2020-04-25 02:16:33 +02:00