devc: add is_done()

libboard_zynq/src/devc/mod.rs

@@ -26,12 +26,18 @@ impl DevC {
         })
     }
 
+    pub fn is_done(&self) -> bool {
+        // Note: contrary to what the TRM says, this appears to be simply
+        // the state of the DONE signal.
+        self.regs.int_sts.read().ixr_pcfg_done()
+    }
+
     pub fn program(&mut self) {
         slcr::RegisterBlock::unlocked(|slcr| {
             slcr.init_preload_fpga();
         });
 
-        while !self.regs.int_sts.read().ixr_pcfg_done() {}
+        while !self.is_done() {}
 
         slcr::RegisterBlock::unlocked(|slcr| {
             slcr.init_postload_fpga();