libboard_zynq: fix access to "full" 1022 MB on target_zc706
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@ -183,6 +183,14 @@ impl DdrRam {
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/// Reset DDR controller
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fn reset_ddrc(&mut self) {
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#[cfg(feature = "target_zc706")]
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unsafe {
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// row/column address bits
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self.regs.dram_addr_map_bank.write(0x00000777);
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self.regs.dram_addr_map_col.write(0xFFF00000);
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self.regs.dram_addr_map_row.write(0x0F666666);
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}
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#[cfg(feature = "target_zc706")]
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let width = regs::DataBusWidth::Width32bit;
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#[cfg(feature = "target_cora_z7_10")]
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@ -209,9 +217,11 @@ impl DdrRam {
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0x0010_0000 as *mut _
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}
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/// actually there's 1 MB more but starting at 0x0000_0000
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/// overlaps with OCM.
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pub fn size(&self) -> usize {
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#[cfg(feature = "target_zc706")]
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let megabytes = 511;
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let megabytes = 1022;
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#[cfg(feature = "target_cora_z7_10")]
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let megabytes = 511;
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