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Donald Sebastian Leung a515938780 Add BGEU instruction 2020-08-11 16:57:34 +08:00
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Insn.py Add generic instruction class 2020-08-07 12:28:52 +08:00
InsnAdd.py Remove redundancy in super() calls 2020-08-10 11:15:05 +08:00
InsnAddi.py Add SLTI instruction 2020-08-10 17:24:50 +08:00
InsnAnd.py Remove redundancy in super() calls 2020-08-10 11:15:05 +08:00
InsnAndi.py Add ANDI instruction 2020-08-10 17:35:43 +08:00
InsnBeq.py Add BEQ instruction 2020-08-11 16:46:07 +08:00
InsnBge.py Add BGE instruction 2020-08-11 16:54:16 +08:00
InsnBgeu.py Add BGEU instruction 2020-08-11 16:57:34 +08:00
InsnBlt.py Add BLT instruction 2020-08-11 16:52:34 +08:00
InsnBltu.py Add BLTU instruction 2020-08-11 16:55:58 +08:00
InsnBne.py Add BNE instruction 2020-08-11 16:49:25 +08:00
InsnJalr.py Add JALR instruction 2020-08-10 14:13:25 +08:00
InsnLb.py Add LB instruction 2020-08-10 16:26:29 +08:00
InsnLbu.py Add LBU instruction 2020-08-10 16:40:45 +08:00
InsnLh.py Add LH instruction 2020-08-10 16:29:42 +08:00
InsnLhu.py Add LHU instruction 2020-08-10 16:44:08 +08:00
InsnLw.py Add LW instruction 2020-08-10 16:35:37 +08:00
InsnOr.py Remove redundancy in super() calls 2020-08-10 11:15:05 +08:00
InsnOri.py Add ORI instruction 2020-08-10 17:34:22 +08:00
InsnRV32IIType.py Add (generic) RV32I I-Type Instruction 2020-08-10 13:32:04 +08:00
InsnRV32IITypeArith.py Add RV32I I-Type Instruction (Arithmetic Variation) 2020-08-10 17:12:09 +08:00
InsnRV32IITypeLoad.py Add LW instruction 2020-08-10 16:35:37 +08:00
InsnRV32IITypeShift.py Remove redundancy in super() calls 2020-08-10 11:15:05 +08:00
InsnRV32IRType.py Remove redundancy in super() calls 2020-08-10 11:15:05 +08:00
InsnRV32ISBType.py Add RV32I SB-Type Instruction Format 2020-08-11 16:37:42 +08:00
InsnRV32ISType.py Add RV32I S-Type Instruction Format 2020-08-11 14:00:04 +08:00
InsnSb.py Add SB instruction 2020-08-11 14:50:04 +08:00
InsnSh.py Add SH instruction 2020-08-11 14:51:34 +08:00
InsnSll.py Remove redundancy in super() calls 2020-08-10 11:15:05 +08:00
InsnSlli.py Fix SLLI instruction 2020-08-10 12:31:20 +08:00
InsnSlt.py Remove redundancy in super() calls 2020-08-10 11:15:05 +08:00
InsnSlti.py Add SLTI instruction 2020-08-10 17:24:50 +08:00
InsnSltiu.py Add SLTIU instruction 2020-08-10 17:29:55 +08:00
InsnSltu.py Remove redundancy in super() calls 2020-08-10 11:15:05 +08:00
InsnSra.py Add attribution to SO in InsnSra.py 2020-08-10 12:46:09 +08:00
InsnSrai.py Add SRAI instruction 2020-08-10 12:56:19 +08:00
InsnSrl.py Remove redundancy in super() calls 2020-08-10 11:15:05 +08:00
InsnSrli.py Add SRLI instruction 2020-08-10 12:35:49 +08:00
InsnSub.py Remove redundancy in super() calls 2020-08-10 11:15:05 +08:00
InsnSw.py Add SW instruction 2020-08-11 14:52:59 +08:00
InsnXor.py Remove redundancy in super() calls 2020-08-10 11:15:05 +08:00
InsnXori.py Add XORI instruction 2020-08-10 17:32:55 +08:00
README.md Update README.md 2020-08-11 14:54:27 +08:00

README.md

RISC-V Instructions

Instructions

Below is a table of RISC-V instructions supported by the original riscv-formal framework at the time of writing, categorized by instruction type.

Instruction type Instructions
R-type ADD, ADDW, AND, DIV, DIVU, DIVUW, DIVW, MUL, MULH, MULHSU, MULHU, MULW, OR, REM, REMU, REMUW, REMW, SLL, SLLW, SLT, SLTU, SRA, SRAW, SRL, SRLW, SUB, SUBW, XOR
I-type ADDI, ADDIW, ANDI, JALR, LB, LBU, LD, LH, LHU, LW, LWU, ORI, SLTI, SLTIU, XORI
I-type (shift variation) SLLI, SLLIW, SRAI, SRAIW, SRLI, SRLIW
S-type SB, SD, SH, SW
SB-type BEQ, BGE, BGEU, BLT, BLTU, BNE
U-type AUIPC, LUI
UJ-type JAL
CI-type C_ADD, C_ADDI, C_ADDIW, C_JALR, C_JR, C_LI, C_MV
CI-type (SP variation) C_ADDI16SP
CI-type (ANDI variation) C_ANDI
CI-type (LSP variation, 32 bit version) C_LWSP
CI-type (LSP variation, 64 bit version) C_LDSP
CI-type (LUI variation) C_LUI
CI-type (SLI variation) C_SLLI
CI-type (SRI variation) C_SRAI, C_SRLI
CIW-type C_ADDI4SPN
CS-type (ALU version) C_ADDW, C_AND, C_OR, C_SUB, C_SUBW, C_XOR
CS-type (32 bit version) C_SW
CS-type (64 bit version) C_SD
CSS-type (32 bit version) C_SWSP
CSS-type (64 bit version) C_SDSP
CB-type C_BEQZ, C_BNEZ
CJ-type C_J, C_JAL
CL-type (32 bit version) C_LW
CL-type (64 bit version) C_LD

Class Synopsis

Below is a list of instructions currently supported by this port of the riscv-formal framework and is expected to grow over time. The instructions are roughly grouped by instruction type but sometimes with further specializations - the hierarchy of the lists reflects the hierarchy of inheritance in the classes used to represent various instructions.

  • Insn: General RISC-V instruction
    • InsnRV32IRType: RV32I R-Type Instruction
      • InsnAdd: ADD instruction
      • InsnSub: SUB instruction
      • InsnSll: SLL instruction
      • InsnSlt: SLT instruction
      • InsnSltu: SLTU instruction
      • InsnXor: XOR instruction
      • InsnSrl: SRL instruction
      • InsnSra: SRA instruction
      • InsnOr: OR instruction
      • InsnAnd: AND instruction
    • InsnRV32IITypeShift: RV32I I-Type Instruction (Shift Variation)
      • InsnSlli: SLLI instruction
      • InsnSrli: SRLI instruction
      • InsnSrai: SRAI instruction
    • InsnRV32IIType: RV32I I-Type Instruction
      • InsnJalr: JALR instruction
      • InsnRV32IITypeLoad: RV32I I-Type Instruction (Load Variation)
        • InsnLb: LB instruction
        • InsnLh: LH instruction
        • InsnLw: LW instruction
        • InsnLbu: LBU instruction
        • InsnLhu: LHU instruction
      • InsnRV32IITypeArith: RV32I I-Type Instruction (Arithmetic Variation)
        • InsnAddi: ADDI instruction
        • InsnSlti: SLTI instruction
        • InsnSltiu: SLTIU instruction
        • InsnXori: XORI instruction
        • InsnOri: ORI instruction
        • InsnAndi: ANDI instruction
    • InsnRV32ISType: RV32I S-Type Instruction
      • InsnSb: SB instruction
      • InsnSh: SH instruction
      • InsnSw: SW instruction

Parameters

TODO