riscv-formal-nmigen/insns/README.md

# RISC-V Instructions

## Instructions

Below is a table of RISC-V instructions supported by the original riscv-formal framework at the time of writing, categorized by instruction type.

| Instruction type | Instructions |
| --- | --- |
| R-type | ADD, ADDW, AND, DIV, DIVU, DIVUW, DIVW, MUL, MULH, MULHSU, MULHU, MULW, OR, REM, REMU, REMUW, REMW, SLL, SLLW, SLT, SLTU, SRA, SRAW, SRL, SRLW, SUB, SUBW, XOR |
| I-type | ADDI, ADDIW, ANDI, JALR, LB, LBU, LD, LH, LHU, LW, LWU, ORI, SLTI, SLTIU, XORI |
| I-type (shift variation) | SLLI, SLLIW, SRAI, SRAIW, SRLI, SRLIW |
| S-type | SB, SD, SH, SW |
| SB-type | BEQ, BGE, BGEU, BLT, BLTU, BNE |
| U-type | AUIPC, LUI |
| UJ-type | JAL |
| CI-type | C\_ADD, C\_ADDI, C\_ADDIW, C\_JALR, C\_JR, C\_LI, C\_MV |
| CI-type (SP variation) | C\_ADDI16SP |
| CI-type (ANDI variation) | C\_ANDI |
| CI-type (LSP variation, 32 bit version) | C\_LWSP |
| CI-type (LSP variation, 64 bit version) | C\_LDSP |
| CI-type (LUI variation) | C\_LUI |
| CI-type (SLI variation) | C\_SLLI |
| CI-type (SRI variation) | C\_SRAI, C\_SRLI |
| CIW-type | C\_ADDI4SPN |
| CS-type (ALU version) | C\_ADDW, C\_AND, C\_OR, C\_SUB, C\_SUBW, C\_XOR |
| CS-type (32 bit version) | C\_SW |
| CS-type (64 bit version) | C\_SD |
| CSS-type (32 bit version) | C\_SWSP |
| CSS-type (64 bit version) | C\_SDSP |
| CB-type | C\_BEQZ, C\_BNEZ |
| CJ-type | C\_J, C\_JAL |
| CL-type (32 bit version) | C\_LW |
| CL-type (64 bit version) | C\_LD |

## Class Synopsis

### Instructions

Below is a list of instructions currently supported by this port of the riscv-formal framework and is expected to grow over time. The instructions are roughly grouped by instruction type but sometimes with further specializations - the hierarchy of the lists reflects the hierarchy of inheritance in the classes used to represent various instructions.

- `Insn`: General RISC-V instruction
  - `InsnRV32IRType`: RV32I R-Type Instruction
    - `InsnAdd`: ADD instruction
    - `InsnSub`: SUB instruction
    - `InsnSll`: SLL instruction
    - `InsnSlt`: SLT instruction
    - `InsnSltu`: SLTU instruction
    - `InsnXor`: XOR instruction
    - `InsnSrl`: SRL instruction
    - `InsnSra`: SRA instruction
    - `InsnOr`: OR instruction
    - `InsnAnd`: AND instruction
  - `InsnRV32IITypeShift`: RV32I I-Type Instruction (Shift Variation)
    - `InsnSlli`: SLLI instruction
    - `InsnSrli`: SRLI instruction
    - `InsnSrai`: SRAI instruction
  - `InsnRV32IIType`: RV32I I-Type Instruction
    - `InsnJalr`: JALR instruction
    - `InsnRV32IITypeLoad`: RV32I I-Type Instruction (Load Variation)
      - `InsnLb`: LB instruction
      - `InsnLh`: LH instruction
      - `InsnLw`: LW instruction
      - `InsnLbu`: LBU instruction
      - `InsnLhu`: LHU instruction
    - `InsnRV32IITypeArith`: RV32I I-Type Instruction (Arithmetic Variation)
      - `InsnAddi`: ADDI instruction
      - `InsnSlti`: SLTI instruction
      - `InsnSltiu`: SLTIU instruction
      - `InsnXori`: XORI instruction
      - `InsnOri`: ORI instruction
      - `InsnAndi`: ANDI instruction
  - `InsnRV32ISType`: RV32I S-Type Instruction
    - `InsnSb`: SB instruction
    - `InsnSh`: SH instruction
    - `InsnSw`: SW instruction
  - `InsnRV32ISBType`: RV32I SB-Type Instruction
    - `InsnBeq`: BEQ instruction
    - `InsnBne`: BNE instruction
    - `InsnBlt`: BLT instruction
    - `InsnBge`: BGE instruction
    - `InsnBltu`: BLTU instruction
    - `InsnBgeu`: BGEU instruction
  - `InsnJal`: JAL instruction
  - `InsnRV32IUType`: RV32I U-Type Instruction
    - `InsnLui`: LUI instruction
    - `InsnAuipc`: AUIPC instruction

### ISAs

TODO

## Core-specific constants

The following core-specific constants are currently supported:

| Constant | Description | Valid value(s) | Supported by instruction(s) |
| --- | --- | --- | --- |
| `RISCV_FORMAL_ILEN` | Max length of instruction retired by core | `32` | LUI, AUIPC, JAL, JALR, BEQ, BNE, BLT, BGE, BLTU, BGEU, LB, LH, LW, LBU, LHU, SB, SH, SW, ADDI, SLTI, SLTIU, XORI, ORI, ANDI, SLLI, SRLI, SRAI, ADD, SUB, SLL, SLT, SLTU, XOR, SRL, SRA, OR, AND |
| `RISCV_FORMAL_XLEN` | Width of integer registers | `32` | LUI, AUIPC, JAL, JALR, BEQ, BNE, BLT, BGE, BLTU, BGEU, LB, LH, LW, LBU, LHU, SB, SH, SW, ADDI, SLTI, SLTIU, XORI, ORI, ANDI, SLLI, SRLI, SRAI, ADD, SUB, SLL, SLT, SLTU, XOR, SRL, SRA, OR, AND |
| `RISCV_FORMAL_CSR_MISA` | Support for MISA CSRs enabled | `True`, `False` | LUI, AUIPC, JAL, JALR, BEQ, BNE, BLT, BGE, BLTU, BGEU, LB, LH, LW, LBU, LHU, SB, SH, SW, ADDI, SLTI, SLTIU, XORI, ORI, ANDI, SLLI, SRLI, SRAI, ADD, SUB, SLL, SLT, SLTU, XOR, SRL, SRA, OR, AND |
| `RISCV_FORMAL_COMPRESSED` | Support for compressed instructions | `True`, `False` | JAL, JALR, BEQ, BNE, BLT, BGE, BLTU, BGEU |
| `RISCV_FORMAL_ALIGNED_MEM` | Require aligned memory accesses | `True`, `False` | LB, LH, LW, LBU, LHU, SB, SH, SW |