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Donald Sebastian Leung 2020-08-11 10:08:11 +08:00
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# RISC-V Supported Instructions
# RISC-V Instructions
## Instructions
Below is a table of RISC-V instructions supported by the original riscv-formal framework at the time of writing, categorized by instruction type.
| Instruction type | Instructions |
| --- | --- |
| R-type | ADD, ADDW, AND, DIV, DIVU, DIVUW, DIVW, MUL, MULH, MULHSU, MULHU, MULW, OR, REM, REMU, REMUW, REMW, SLL, SLLW, SLT, SLTU, SRA, SRAW, SRL, SRLW, SUB, SUBW, XOR |
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## Class Synopsis
_Note: This section is under development and will be updated as more classes are implemented._
Below is a list of instructions currently supported by this port of the riscv-formal framework and is expected to grow over time. The instructions are roughly grouped by instruction type but sometimes with further specializations - the hierarchy of the lists reflects the hierarchy of inheritance in the classes used to represent various instructions.
- `Insn`: General RISC-V instruction
- `InsnRV32IRType`: RV32I R-Type Instruction