riscv-formal-nmigen/insns/README.md

# RISC-V Supported Instructions

## Instructions

| Instruction type | Instructions |
| --- | --- |
| R-type | ADD, ADDW, AND, DIV, DIVU, DIVUW, DIVW, MUL, MULH, MULHSU, MULHU, MULW, OR, REM, REMU, REMUW, REMW, SLL, SLLW, SLT, SLTU, SRA, SRAW, SRL, SRLW, SUB, SUBW, XOR |
| I-type | ADDI, ADDIW, ANDI, JALR, LB, LBU, LD, LH, LHU, LW, LWU, ORI, SLTI, SLTIU, XORI |
| I-type (shift variation) | SLLI, SLLIW, SRAI, SRAIW, SRLI, SRLIW |
| S-type | SB, SD, SH, SW |
| SB-type | BEQ, BGE, BGEU, BLT, BLTU, BNE |
| U-type | AUIPC, LUI |
| UJ-type | JAL |
| CI-type | C\_ADD, C\_ADDI, C\_ADDIW, C\_JALR, C\_JR, C\_LI, C\_MV |
| CI-type (SP variation) | C\_ADDI16SP |
| CI-type (ANDI variation) | C\_ANDI |
| CI-type (LSP variation, 32 bit version) | C\_LWSP |
| CI-type (LSP variation, 64 bit version) | C\_LDSP |
| CI-type (LUI variation) | C\_LUI |
| CI-type (SLI variation) | C\_SLLI |
| CI-type (SRI variation) | C\_SRAI, C\_SRLI |
| CIW-type | C\_ADDI4SPN |
| CS-type (ALU version) | C\_ADDW, C\_AND, C\_OR, C\_SUB, C\_SUBW, C\_XOR |
| CS-type (32 bit version) | C\_SW |
| CS-type (64 bit version) | C\_SD |
| CSS-type (32 bit version) | C\_SWSP |
| CSS-type (64 bit version) | C\_SDSP |
| CB-type | C\_BEQZ, C\_BNEZ |
| CJ-type | C\_J, C\_JAL |
| CL-type (32 bit version) | C\_LW |
| CL-type (64 bit version) | C\_LD |

## Class Synopsis

_Note: This section is under development and will be updated as more classes are implemented._

- `Insn`: General RISC-V instruction
  - `InsnRV32IRType`: RV32I R-Type Instruction
    - `InsnAdd`: ADD instruction
    - `InsnSub`: SUB instruction
    - `InsnSll`: SLL instruction
    - `InsnSlt`: SLT instruction
    - `InsnSltu`: SLTU instruction
    - `InsnXor`: XOR instruction
    - `InsnSrl`: SRL instruction
    - `InsnSra`: SRA instruction
    - `InsnOr`: OR instruction
    - `InsnAnd`: AND instruction
  - `InsnRV32IITypeShift`: RV32I I-Type Instruction (Shift Variation)
    - `InsnSlli`: SLLI instruction
    - `InsnSrli`: SRLI instruction
    - `InsnSrai`: SRAI instruction
  - `InsnRV32IIType`: RV32I I-Type Instruction
    - `InsnJalr`: JALR instruction
    - `InsnRV32IITypeLoad`: RV32I I-Type Instruction (Load Variation)
      - `InsnLb`: LB instruction
      - `InsnLh`: LH instruction
      - `InsnLw`: LW instruction
      - `InsnLbu`: LBU instruction
      - `InsnLhu`: LHU instruction

## Parameters

TODO