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mirror of https://github.com/m-labs/artiq.git synced 2025-01-26 18:38:13 +08:00
artiq/artiq/gateware/rtio
2022-11-01 08:12:54 +08:00
..
phy rtio: remove rtio clock, use sys instead 2022-11-01 08:12:54 +08:00
sed rtio: remove rtio clock, use sys instead 2022-11-01 08:12:54 +08:00
__init__.py cri: fix firmware routing table access 2018-09-12 18:08:16 +08:00
analyzer.py dma: set conversion granularity using bus width 2021-11-08 16:59:08 +08:00
cdc.py rtio: remove rtio clock, use sys instead 2022-11-01 08:12:54 +08:00
channel.py use FutureWarning instead of DeprecationWarning 2018-10-21 12:14:51 +08:00
core.py rtio: remove rtio clock, use sys instead 2022-11-01 08:12:54 +08:00
cri.py rtio: remove rtio clock, use sys instead 2022-11-01 08:12:54 +08:00
dma.py dma: set conversion granularity using bus width 2021-11-08 16:59:08 +08:00
input_collector.py rtio: remove rtio clock, use sys instead 2022-11-01 08:12:54 +08:00
moninj.py moninj: do not require a rsys clock domain 2017-02-20 15:52:48 +08:00
rtlink.py rtlink: sanity-check parameters 2018-11-26 01:14:02 +08:00
tsc.py rtio: remove rtio clock, use sys instead 2022-11-01 08:12:54 +08:00
xilinx_clocking.py rtio: remove rtio clock, use sys instead 2022-11-01 08:12:54 +08:00