mirror of https://github.com/m-labs/artiq.git
49 lines
1.4 KiB
Python
49 lines
1.4 KiB
Python
from migen import *
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from artiq.gateware.rtio.cdc import GrayCodeTransfer
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class TSC(Module):
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def __init__(self, mode, glbl_fine_ts_width=0):
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self.glbl_fine_ts_width = glbl_fine_ts_width
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# in rtio domain
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self.coarse_ts = Signal(64 - glbl_fine_ts_width)
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self.full_ts = Signal(64)
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# in sys domain
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# monotonic, may lag behind the counter in the IO clock domain, but
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# not be ahead of it.
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self.coarse_ts_sys = Signal.like(self.coarse_ts)
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self.full_ts_sys = Signal(64)
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# in rtio domain
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self.load = Signal()
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self.load_value = Signal.like(self.coarse_ts)
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if mode == "async":
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self.full_ts_cri = self.full_ts_sys
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elif mode == "sync":
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self.full_ts_cri = self.full_ts
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else:
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raise ValueError
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# # #
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self.sync += If(self.load,
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self.coarse_ts.eq(self.load_value)
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).Else(
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self.coarse_ts.eq(self.coarse_ts + 1)
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)
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coarse_ts_cdc = GrayCodeTransfer(len(self.coarse_ts)) # from rtio to sys
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self.submodules += coarse_ts_cdc
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self.comb += [
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coarse_ts_cdc.i.eq(self.coarse_ts),
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self.coarse_ts_sys.eq(coarse_ts_cdc.o)
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]
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self.comb += [
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self.full_ts.eq(self.coarse_ts << glbl_fine_ts_width),
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self.full_ts_sys.eq(self.coarse_ts_sys << glbl_fine_ts_width)
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]
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