artiq/artiq/gateware
Sebastien Bourdeauducq 92fd705990 increase memory allocated to comms CPU
See discussion in #1612.
2021-02-21 19:06:12 +08:00
..
amp increase memory allocated to comms CPU 2021-02-21 19:06:12 +08:00
drtio wrpll: separate collector reset 2020-11-09 17:57:13 +08:00
dsp sawg: don't use Cat() for signed signals 2018-06-09 07:33:47 +00:00
grabber grabber: fix frame size off-by-1 2018-09-07 16:55:43 +02:00
rtio ttl_serdes_7series: add dci (HP bank) support 2021-02-07 22:32:18 +08:00
suservo suservo: support operating with one urukul 2019-12-02 11:30:20 +01:00
targets metlino,sayma: adapt to new EEM API 2021-02-10 15:32:10 +08:00
test Merge pull request #1533 from m-labs/phaser 2020-10-19 09:30:12 +02:00
__init__.py artiqlib -> artiq.gateware 2015-03-08 11:00:24 +01:00
ad9_dds.py ad9xxx -> ad9_dds 2017-01-04 11:34:52 +01:00
eem.py eem: fix Urukul QSPI after 9ef5717de8 (2) 2021-02-12 13:17:48 +08:00
eem_7series.py eem_7series: pass through kwargs 2021-02-10 15:31:49 +08:00
fmcdio_vhdci_eem.py fmcdio_vhdci_eem: fix pin naming 2020-08-31 16:21:45 +08:00
jesd204_tools.py jesd204_tools: use new syntax from jesd204b core 2020-12-19 17:05:20 +08:00
nist_clock.py gateware/nist_clock: increase DDS bus drive strength. Closes #468 2016-06-07 11:08:19 -04:00
nist_qc2.py qc2: swap SPI/TTL, all TTL lines are now In+Out compatible 2016-05-19 10:42:03 +08:00