Spaqin
8be945d5c7
Urukul monitoring ( #1142 , #1921 )
2022-07-07 10:52:53 +08:00
Spaqin
35f30ddf05
Expose TTLClockGen for Kasli JSONs ( #1886 )
2022-05-06 13:33:42 +08:00
Leon Riesebos
c4292770f8
Kasli JSON description for SPI over DIO cards ( #1800 )
2022-02-26 07:36:00 +08:00
Mikołaj Sowiński
898122f3e5
Added support for HVAMP_8CH ( #1741 )
2021-08-16 13:39:00 +08:00
Sebastien Bourdeauducq
d33a206f04
eem: fix Urukul QSPI after 9ef5717de8
(2)
2021-02-12 13:17:48 +08:00
Sebastien Bourdeauducq
22ce5b0299
eem: fix Urukul QSPI after 9ef5717de8
2021-02-12 10:59:53 +08:00
Sebastien Bourdeauducq
49299c00a9
eem: enable DCI for LVDS TTL
2021-02-10 15:31:25 +08:00
Sebastien Bourdeauducq
9ef5717de8
eem: support different I/O standards in EEM slots
2021-02-10 15:31:05 +08:00
Sebastien Bourdeauducq
bfacd1e5b3
eem: fix Grabber cc_0-2 signal definitions
2021-02-07 18:01:05 +08:00
Robert Jördens
50b4eb4840
Merge branch 'master' into phaser
...
* master: (26 commits)
fastino: documentation and eem pass-through
kasli2: forward sma_clkin to si5324
test: relax test_dma_playback_time on Zynq
rpc: fixed _write_bool
fastino: document/cleanup
build_soc: remove assertion that was used for test runs
metlino_sayma_ttl: Fix RTIO frequency & demo code (#1516 )
Revert "test: temporarily disable test_async_throughput"
build_soc: rename identifier_str to gateware_identifier_str
test: relax loopback gate timing
test: temporarily disable test_async_throughput
test: relax test_pulse_rate on Zynq
test: skip NonexistentI2CBus if I2C is not supported
build_soc: override identifier_str only for gateware
examples: add Metlino master, Sayma satellite with TTLOuts via FMC
sayma_amc: add support for 4x DIO output channels via FMC
fmcdio_vhdci_eem: fix pin naming
build_soc: add identifier_str override option
RPC: optimization by caching
test: improved test_performance
...
2020-09-22 16:02:25 +00:00
Robert Jördens
c55f2222dc
fastino: documentation and eem pass-through
...
* Repeat information about matching log2_width a few times
in the hope that people read it. #1518
* Pass through log2_width in kasli_generic json. close #1481
* Check DAC value range. #1518
2020-09-22 17:58:53 +02:00
Robert Jördens
c18f515bf9
phaser: rework rtio channels, sync_dly, init()
2020-09-16 12:23:07 +00:00
Robert Jördens
e5e2392240
phaser: wire up multidds
2020-08-26 17:12:41 +00:00
Robert Jördens
d1be1212ab
phaser: coredevice shim, dds [wip]
2020-08-26 15:10:50 +00:00
Robert Jördens
aa0154d8e2
phaser: initial
2020-08-22 11:56:23 +00:00
Robert Jördens
e803830b3b
fastino: support wide RTIO interface and channel groups
2020-03-05 17:55:04 +00:00
Robert Jördens
2c4e5bfee4
fastino: add [WIP]
2020-01-20 13:25:00 +01:00
Robert Jördens
01a6e77d89
mirny: add
...
* This targets unrelease CPLD gateware (https://github.com/quartiq/mirny/issues/1 )
* includes initial coredevice driver, eem shims, and kasli_generic tooling
* addresses the ARTIQ side of #1130
* Register abstraction to be written
Signed-off-by: Robert Jördens <rj@quartiq.de>
2020-01-20 13:13:08 +01:00
Robert Jördens
05c5fed07d
suservo: stray comma
2019-12-03 08:38:07 +00:00
Robert Jördens
56074cfffa
suservo: support operating with one urukul
...
implemented by wiring up the second Urukul to dummy pins
Signed-off-by: Robert Jördens <rj@quartiq.de>
2019-12-02 11:30:20 +01:00
David Nadlinger
bc3b55b1a8
gateware/eem: Force IOB=TRUE on Urukul SYNC output
...
Without this, the final register in the SYNC signal TTLClockGen
isn't (always) placed in the I/O tile, leading to more jitter
than necessary, and causing "double window" artefacts. See
sinara-hw/Urukul#16 for more details.
(Patch based on work by Weida Zhang, testing by various members
of the community in Oxford and elsewhere.)
2019-11-05 17:14:07 +08:00
Sebastien Bourdeauducq
991c686d72
kasli_generic,eem: print RTIO channels in hex like artiq_ddb_template
2019-09-11 15:51:53 +08:00
Sebastien Bourdeauducq
1fb317778a
eem/grabber: allow third EEM to be specified
2019-08-29 18:58:12 +08:00
David Nadlinger
720838a23e
gateware/suservo: Avoid magic number for activation delay width
...
Mostly for documentation purposes; 8 bits ought to be enough for
everyone.
2019-06-14 23:45:40 +01:00
David Nadlinger
a565f77538
Add gateware input event counter
2019-01-15 10:55:07 +00:00
Robert Jördens
6df4ae934f
eem: name the servo submodule
...
This allows the migen namer to derive names for the ADC return clock
domain in the case of multiple SUServos
close #1201
Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-12-11 11:36:40 +01:00
Robert Jördens
2af6edb8f5
eem: fix reset/sync in suservo
...
Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-13 13:00:54 +00:00
Robert Jördens
3538444876
urukul: add sync_in to eem0-7 name
...
Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-05 19:36:32 +01:00
Robert Jördens
0433e8f4fe
urukul: add sync_in generator
...
for #1143
Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-05 19:36:30 +01:00
Sebastien Bourdeauducq
9b016dcd6d
eem: support specifying I/O standard
...
Xilinx FPGAs require different LVDS I/O standard names depending on I/O bank voltage.
2018-07-17 18:55:17 +08:00
Sebastien Bourdeauducq
b6c70b3cb0
eem: add Zotino monitoring. Closes #1095
2018-07-15 15:35:04 +08:00
Sebastien Bourdeauducq
701c93d46c
grabber: add false path constraints
2018-07-10 14:28:23 +08:00
Sebastien Bourdeauducq
c4e3c66265
grabber: add clock constraint
2018-07-10 12:37:32 +08:00
Sebastien Bourdeauducq
540bdae99c
grabber: enable DIFF_TERM on inputs
2018-07-01 09:28:51 +08:00
Robert Jördens
bb87976d4f
suservo: docstring fixes, revert parametrization of r_rtt
2018-06-04 07:27:17 +00:00
Robert Jördens
07a1425e51
SUservo EEM docs
...
add documentation to eem.SUServo. Change parameterization of t_rtt to include delays on Sampler, as this seems simpler and more robust to changing RTIO frequencies in the future.
c.f. #1046
2018-06-04 08:51:28 +02:00
Robert Jördens
f50aef1a22
suservo: extract boilerplate
...
closes #1041
2018-06-01 15:37:07 +00:00
Sebastien Bourdeauducq
563e434e15
eem: finalize grabber support
2018-05-28 22:43:06 +08:00
Sebastien Bourdeauducq
80c69da17e
eem: add Grabber IOs and CC
2018-05-28 11:16:23 +08:00
Sebastien Bourdeauducq
bb248970df
style
2018-05-28 10:40:05 +08:00
Sebastien Bourdeauducq
19efd8b13e
kasli: refactor EEM code
2018-05-24 18:41:54 +08:00