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mirror of https://github.com/m-labs/artiq.git synced 2024-12-21 09:26:29 +08:00
Commit Graph

5237 Commits

Author SHA1 Message Date
whitequark
a07bd918f0 firmware: use Rust naming conventions for enum variants. 2017-02-25 22:34:11 +00:00
whitequark
2a81819eb0 firmware: restructure to avoid #[path = "..."] mod ...;
Such code is fragile, introduces mess in dependencies, and
inflates compile times.
2017-02-25 17:54:14 +00:00
whitequark
d04e611232 firmware, compiler: rename rpc functions to be more consistent. 2017-02-25 14:12:58 +00:00
e82ce3ea28 coredevice: ignore .dirty in version checks correctly 2017-02-25 20:05:05 +08:00
98be556143 drtioaux: fix compiler warnings 2017-02-25 12:18:57 +08:00
f017d1771f gateware: remove unused configs in targets (not needed with new moninj) 2017-02-25 12:14:56 +08:00
5a16660aa2 runtime: new moninj protocol, TCP-based, with DRTIO support 2017-02-25 12:07:00 +08:00
1486a945d9 manual: update moninj network info 2017-02-25 12:06:35 +08:00
7d568b4bac style 2017-02-25 12:06:12 +08:00
whitequark
13c6e96760 firmware: implement dyld::Library::rebind. 2017-02-25 00:10:40 +00:00
whitequark
04ad267055 firmware: rewrite the dynamic linker in Rust. 2017-02-24 18:57:29 +00:00
360be0098f drtio: map local RTIO core on lower channels 2017-02-24 18:15:27 +08:00
whitequark
907589fb58 satman: simplify Makefile. 2017-02-23 10:29:25 +00:00
whitequark
623a605d3b satman: refactor type conversions. 2017-02-23 08:59:27 +00:00
b34c6ba6b9 satman: process moninj packets 2017-02-23 16:24:05 +08:00
45ac0dcf57 drtioaux: add moninj packets 2017-02-23 16:23:51 +08:00
016743f079 libdrtioaux: do not attempt to access non-existent DRTIO gateware 2017-02-22 16:45:02 +08:00
257527629a firmware: use aux ping to determine when DRTIO satellite is ready 2017-02-22 15:26:32 +08:00
a8ea557406 firmware: add DRTIO aux packet library (WIP) 2017-02-21 21:55:36 +08:00
b455ea447d gateware: add moninj to drtio targets 2017-02-21 21:54:47 +08:00
whitequark
a12876b239 firmware: update Cargo.lock. 2017-02-21 05:28:48 +00:00
whitequark
1dabe05c5a artiq_devtool: add clean command and --config option. 2017-02-21 05:28:19 +00:00
whitequark
b468959e14 doc: manual/developing: update binutils patch URL. 2017-02-21 05:28:19 +00:00
c66efc0279 moninj: do not require a rsys clock domain 2017-02-20 15:52:48 +08:00
8da28177a4 conda: bump migen 2017-02-20 15:52:05 +08:00
e323e37829 pcu: refactor into a device 2017-02-19 19:34:55 +01:00
b05d1bb7e3 coreanalyzer: fix corner case crash 2017-02-19 19:28:13 +01:00
1573ff5fc1 coreanalyzer: add WB stb signal 2017-02-18 14:53:10 +01:00
039ced6637 coreanalyzer: use VCD scopes for DDS/SPI 2017-02-18 14:25:01 +01:00
7519408857 coreanalyzer: add SPIMaster support 2017-02-18 14:13:20 +01:00
41e8acf3ad coreanalyzer handle input events without timestamp
Offset the timeline by the first non-zero timestamp.
2017-02-18 14:12:02 +01:00
bc3fc26e34 coredevice: expose PCU 2017-02-18 14:09:12 +01:00
3e2dad6573 misoc: bump (mor1kx pcu) 2017-02-18 14:09:12 +01:00
6b5b679659 libboard: PCU regs 2017-02-18 14:09:12 +01:00
c022b53578 kernel_cpu: enable perf counters 2017-02-18 14:09:12 +01:00
9501d37378 firmware: wait longer for Si5324 lock + more monitoring 2017-02-18 17:24:46 +08:00
7e8348a73e si5324: fix error handling 2017-02-18 14:12:18 +08:00
59e79673f7 satman: program Si5324 BWSEL depending on frequency 2017-02-18 14:12:01 +08:00
0bfce37fae satman: do not use Si5324 automatic clock switching
The Si5324 is easily confused by the broken clock generated during link
initialization with BruteforceClockAligner. This commit prevents this problem.
2017-02-18 13:32:40 +08:00
bd55436668 protocols: increase asyncio line limit. Closes #671 2017-02-17 20:46:23 +08:00
whitequark
f4ae166a4c conda: fix syntax. 2017-02-05 16:46:11 +00:00
whitequark
52a046d0fd conda: roll cargo back to 0.11.0, then fix revision of compiler_builtins. 2017-02-05 15:25:43 +00:00
whitequark
3de19f6786 conda: use verbose misoc build. 2017-02-05 14:26:08 +00:00
whitequark
990b642461 conda: bump cargo dependency to >= 0.16.0.
We currently have cargo ignoring and recreating the lockfile on CI,
which is probably caused by it being too old.
2017-02-05 13:55:15 +00:00
whitequark
25c9b8827a firmware: mark __artiq_{re,}raise as #[unwind].
This is required for correctness.
2017-02-05 09:04:22 +00:00
whitequark
6d094eda32 conda: bump rust dependency. 2017-02-05 09:00:45 +00:00
whitequark
f94028b8df Fix c39394b. 2017-02-04 16:23:32 +00:00
3eef0bcc1a firmware: give si5324 more time to lock 2017-02-04 19:19:25 +08:00
935799dfb7 drtio: fix satellite transceiver clocking 2017-02-04 19:18:35 +08:00
whitequark
c39394b4d5 firmware: port the exception handling routines to Rust. 2017-02-04 08:21:07 +00:00