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coreanalyzer: use VCD scopes for DDS/SPI
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parent
7519408857
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039ced6637
@ -1,6 +1,7 @@
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from operator import itemgetter
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from collections import namedtuple
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from itertools import count
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from contextlib import contextmanager
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import struct
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import logging
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@ -118,6 +119,12 @@ class VCDManager:
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.format(name=name, code=code, width=width))
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return VCDChannel(self.out, code)
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@contextmanager
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def scope(self, name):
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self.out.write("$scope module {} $end\n".format(name))
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yield
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self.out.write("$upscope $end\n")
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def set_time(self, time):
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if time != self.current_time:
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self.out.write("#{}\n".format(time))
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@ -178,10 +185,11 @@ class DDSHandler:
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def add_dds_channel(self, name, dds_channel_nr):
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dds_channel = dict()
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dds_channel["vcd_frequency"] = \
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self.vcd_manager.get_channel("dds/" + name + "/frequency", 64)
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dds_channel["vcd_phase"] = \
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self.vcd_manager.get_channel("dds/" + name + "/phase", 64)
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with self.vcd_manager.scope("dds/{}".format(name)):
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dds_channel["vcd_frequency"] = \
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self.vcd_manager.get_channel(name + "/frequency", 64)
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dds_channel["vcd_phase"] = \
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self.vcd_manager.get_channel(name + "/phase", 64)
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if self.dds_type == "DDSChannelAD9914":
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dds_channel["ftw"] = [None, None]
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dds_channel["pow"] = None
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@ -266,12 +274,13 @@ class SPIMasterHandler(WishboneHandlerMixin):
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def __init__(self, vcd_manager, name):
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super().__init__(read_bit=0b100)
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self.channels = {}
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for reg_name, reg_width in [
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("config", 32),
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("chip_select", 16), ("write_length", 8), ("read_length", 8),
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("write", 32), ("read", 32)]:
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self.channels[reg_name] = vcd_manager.get_channel(
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"/".join((name, reg_name)), reg_width)
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with vcd_manager.scope("spi/{}".format(name)):
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for reg_name, reg_width in [
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("config", 32), ("chip_select", 16),
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("write_length", 8), ("read_length", 8),
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("write", 32), ("read", 32)]:
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self.channels[reg_name] = vcd_manager.get_channel(
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"{}/{}".format(name, reg_name), reg_width)
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def process_write(self, address, data):
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if address == 0:
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