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6991 Commits

Author SHA1 Message Date
Sebastien Bourdeauducq ebd5d890f1 satman: check for JESD ready 2019-10-06 23:10:57 +08:00
Sebastien Bourdeauducq 90e3b83e80 hmc7043: turn on AMC_FPGA_SYSREF1 
Florent's JESD core won't work at all without.
 2019-10-06 22:49:00 +08:00
Sebastien Bourdeauducq 97a0dee3e8 jesd204: remove ibuf_disable 
We use the MOSFET to mute the HMC7043 noise on hardware v2 instead.
 2019-10-06 22:26:31 +08:00
Sebastien Bourdeauducq 1bc7743e03 sayma: fix hmc7043 output settings for v2 hardware 2019-10-06 21:50:29 +08:00
Sebastien Bourdeauducq a421820a32 sayma: initialize DACs over DRTIO 2019-10-06 21:42:45 +08:00
Sebastien Bourdeauducq f8e4cc37d0 sayma_rtm: reset and detect DACs 2019-10-06 20:15:27 +08:00
Sebastien Bourdeauducq f62dc7e1d4 sayma: refactor JESD DAC channel groups 2019-10-06 20:15:09 +08:00
Sebastien Bourdeauducq c4c884b8ce ad9154: simplify, focus on AD9154 config and do not include JESD 2019-10-06 20:07:02 +08:00
Sebastien Bourdeauducq fdba0bfbbc satman: move now-unrelated hmc830_7043 init away from DRTIO transceiver init 2019-10-06 19:22:46 +08:00
Sebastien Bourdeauducq 1c6c22fde9 sayma_amc: HMC830_REF moved to RTM side 2019-10-06 18:15:37 +08:00
Sebastien Bourdeauducq ad63908aff hmc830_7043: enable_fpga_ibuf -> unmute 2019-10-06 18:13:59 +08:00
Sebastien Bourdeauducq 5ad65b9d30 hmc830_7043: remove clock_mux 2019-10-06 18:13:27 +08:00
Sebastien Bourdeauducq e6ff44301b sayma_amc: cleanup (v2.0 only) 2019-10-06 18:11:43 +08:00
Sebastien Bourdeauducq e9b81f6e33 remove serwb 
DRTIO is a better solution
 2019-10-06 18:10:23 +08:00
Sebastien Bourdeauducq 7cd02d30b7 sayma_rtm_drtio: replace sayma_rtm 2019-10-06 17:59:53 +08:00
Sebastien Bourdeauducq b3b85135a3 sayma_rtm_drtio: add DDMTD core, move specific cores out of SatelliteBase 2019-10-06 17:59:11 +08:00
Sebastien Bourdeauducq 346c985347 sayma_rtm_drtio: use artiq_sayma folder 2019-10-06 17:30:08 +08:00
Sebastien Bourdeauducq e2a924449d artiq_flash: use DRTIO RTM gateware 2019-10-06 17:28:14 +08:00
Sebastien Bourdeauducq 4198033657 sayma_rtm_drtio: cleanup (v2.0 only) 2019-10-06 16:42:34 +08:00
Sebastien Bourdeauducq 5612b31860 sayma_rtm_drtio: add HMC clock chip and DAC control 2019-10-06 16:15:24 +08:00
Sebastien Bourdeauducq a8cf4c2b18 sayma_rtm: hwrev v2.0 by default 2019-10-06 13:25:30 +08:00
Sebastien Bourdeauducq 1bc5d44a7c artiq_flash: do not flash RTM gateware on Sayma variants that don't need it 2019-10-06 13:15:50 +08:00
Sebastien Bourdeauducq bb5ff46f7d Merge branch 'wrpll' 2019-10-05 10:24:11 +08:00
Sebastien Bourdeauducq 7b95814cf5 sayma_amc: refactor, add SimpleSatellite variant 2019-10-05 10:24:06 +08:00
Sebastien Bourdeauducq 58b7bdcecc sayma_amc: refactor RTM FPGA code 2019-10-05 10:24:06 +08:00
Sebastien Bourdeauducq 96fc4a21e8 sayma_amc: remove dummy FPGA pin assignment testing code 2019-10-05 10:24:06 +08:00
Tim Ballance ada3b39f4e Fix ad9910 ram mode asf scale error in polar mode 2019-10-04 20:14:41 +02:00
Tim Ballance 448080e71d Fix ad9910 ram mode asf scale error 
RAM mode amplitude to ASF conversion should be << 18 rather than << 16
 2019-10-04 20:14:41 +02:00
Sebastien Bourdeauducq 6aa68e1715 sayma_rtm2: select filtered clock from Si5324 2019-10-04 22:56:16 +08:00
Sebastien Bourdeauducq 6cb0f5de59 sayma_amc: enable DRTIO switching 2019-10-04 22:55:23 +08:00
Sebastien Bourdeauducq 0cf8a46bbd sayma_amc2: select filtered clock from Si5324 2019-10-04 21:28:26 +08:00
Sebastien Bourdeauducq 6f533727cb artiq_flash: use regular bscan_spi_xcku040 for Sayma 
The modified version is no longer necessary on v2 boards, and breaks flash bank 1.
 2019-10-04 17:50:45 +08:00
Sebastien Bourdeauducq 4c1fe1de0d environment: implement HasEnvironment.call_child_method (#1366) 2019-09-30 23:58:36 +08:00
Charles Baynham 0b1fb255a9 tools: Wrap Task _do() calls in a generic exception handler 
Signed-off-by: Charles Baynham <charles.baynham@npl.co.uk>
 2019-09-20 23:00:59 +08:00
Charles Baynham e50a6d5aaf worker_impy: ignore newline at start of experiment docstring 2019-09-20 22:10:49 +08:00
Robert Jördens f0e87d2e59 grabber: remove unused code 2019-09-20 15:26:12 +02:00
Sebastien Bourdeauducq 4e77be0511 firmware: add Cargo.lock header that newer cargo wants 2019-09-17 15:22:14 +08:00
Sebastien Bourdeauducq 694b85f37a doc: only one hydra build for conda packages 2019-09-13 09:43:12 +08:00
Charles Baynham b7abf2fb53 pyon: Handle inf in decoding 2019-09-12 09:46:05 +08:00
Sebastien Bourdeauducq 38fca01189 artiq_ddb_template: add su-servo support (#1343) 2019-09-11 15:52:25 +08:00
Sebastien Bourdeauducq 991c686d72 kasli_generic,eem: print RTIO channels in hex like artiq_ddb_template 2019-09-11 15:51:53 +08:00
Robert Jördens f4dd7e5e29 kasli_tester: init urukul channel before calibrating 
Otherwise the DDS is not initialized and with a cold system it fails to
find IO_UPDATE edges.

Signed-off-by: Robert Jördens <rj@quartiq.de>
 2019-09-11 07:16:35 +00:00
Sebastien Bourdeauducq 7492a59f6d kasli_generic: add SUServo support (#1343) 2019-09-11 11:12:48 +08:00
David Nadlinger 6d6f66338b runtime: Update core config panic_reset command suggestion message 2019-09-10 19:31:19 +01:00
Charles Baynham ddd34e5a9c influx_schedule: log repo_rev along with other info 
Signed-off-by: Charles Baynham <charles.baynham@npl.co.uk>
 2019-09-10 13:46:28 +02:00
Sebastien Bourdeauducq 98caaebade consistent use of 'class name' terminology to select a class within an experiment file. Closes #1348 2019-09-09 15:16:33 +08:00
Sebastien Bourdeauducq 21021beb08 kasli: remove opticlock (moved to kasli_generic) 2019-09-09 15:03:10 +08:00
Sebastien Bourdeauducq 436662be52 ddb_template: add Novogorny support 2019-09-09 15:00:45 +08:00
Sebastien Bourdeauducq 69c2acd9d7 ddb_template: sampler cnv is ttl not spi 2019-09-09 14:57:42 +08:00
Sebastien Bourdeauducq cfb5ef5548 kasli_generic: add Novogorny support 2019-09-09 14:54:34 +08:00