whitequark
b6e2613f77
runtime: avoid spurious error messages.
2015-08-07 11:03:36 +03:00
whitequark
b5cf1e395d
runtime: avoid race condition when running kernel.
...
Also, don't bother passing kernel name: entry point is already
recorded in DT_INIT when the kernel is linked.
2015-08-07 08:51:33 +03:00
whitequark
98cd4288c1
artiq_personality: cast exception params so that %lld is always valid.
2015-08-06 08:25:53 +03:00
whitequark
722dfef97b
artiq_personality: simplify.
2015-08-06 07:59:15 +03:00
whitequark
62fdc75d2d
Integrate libdyld and libunwind.
...
It is currently possible to run the idle experiment, and it
can raise and catch exceptions, but exceptions are not yet
propagated across RPC boundaries.
2015-08-02 15:43:03 +03:00
whitequark
6db93b34e8
artiq_personality: port to device.
2015-08-02 06:34:11 +03:00
whitequark
aae2923c4c
runtime: add lognonl{,_va} functions.
...
The kernels have print(), which prints aggregates (such as
arrays) piece-by-piece, and newlines would interfere.
2015-08-02 06:33:12 +03:00
whitequark
cd294e2986
artiq_personality: avoid unaligned loads.
2015-08-02 06:28:58 +03:00
whitequark
697b78ddf2
Rename {kserver → net_server}.{c,h}.
2015-07-30 13:45:57 +03:00
whitequark
fd46d8b11e
Merge branch 'master' into new-py2llvm
2015-07-29 12:52:19 +03:00
whitequark
c40ae9dbd3
MiSoC is not built with -fPIC anymore, remove support code for that.
2015-07-29 12:40:46 +03:00
f0a7078336
Revert "rtiocrg.c: pipistrello also has pll_reset"
...
This reverts commit bdee914828
2015-07-27 22:18:45 -06:00
bdee914828
rtiocrg.c: pipistrello also has pll_reset
2015-07-27 22:14:42 -06:00
ae3a52c49c
runtime: fix KERNELCPU_PAYLOAD_ADDRESS
2015-07-28 02:12:14 +08:00
whitequark
eec4a2d2d2
Update buildsystem to track -fPIC and ranlib removal in MiSoC.
2015-07-27 21:10:46 +03:00
0cd74533ca
runtime: more explicit message about startup clock failure
2015-07-28 00:38:38 +08:00
7feaca7c7c
runtime: allow selecting external clock at startup
2015-07-28 00:19:07 +08:00
09d837e4ba
runtime: monitor RTIO clock status
2015-07-28 00:05:24 +08:00
fe57308e71
runtime: support for RTIO PLL
2015-07-27 20:11:31 +08:00
whitequark
244ace19e1
Add artiq_raise_from_c macro.
2015-07-27 13:56:18 +03:00
whitequark
edffb40ef2
On uncaught exception, execute finally clauses and collect backtrace.
2015-07-27 13:51:24 +03:00
whitequark
2939d4f0f3
Add tests for finally clause and reraising.
2015-07-27 12:36:21 +03:00
whitequark
a83e7e2248
Add tests for exceptional control flow.
2015-07-27 10:22:28 +03:00
whitequark
7c77dd317a
Implement __artiq_personality.
2015-07-27 09:10:20 +03:00
117b361a06
Merge branch 'master' of github.com:m-labs/artiq
2015-07-27 11:42:29 +08:00
d3f05e414a
runtime: account for RTIO_FINE_TS_WIDTH in time buffers
2015-07-27 10:50:25 +08:00
whitequark
bb5fe60137
Implement exception raising.
2015-07-27 05:46:43 +03:00
whitequark
14c7b15785
Add a test harness for exceptions.
...
The libunwind.h is duplicated here so that it would be possible
to test the Python parts without pulling in misoc.
2015-07-27 04:18:12 +03:00
whitequark
1d9f40833d
Update ldscripts with -fPIC support.
2015-07-26 16:16:48 +03:00
aba2d3f112
runtime: process essential kernel CPU messages at all time
2015-07-25 16:26:04 +08:00
34aacd3c5f
complete AD9914 support (no programmable modulus, untested)
2015-07-08 17:22:43 +02:00
8a33d8c868
never stop RTIO counter
2015-07-07 15:29:38 +02:00
d20fb5abb2
remove workaround
2015-07-07 13:46:14 +02:00
753d61b38f
complete support for TTL clock generator
2015-07-04 18:36:01 +02:00
944bfafefa
soc: support QC2 and AD9914 (untested)
2015-06-28 21:37:27 +02:00
b6310b72db
runtime: fix log formatting
2015-06-28 17:29:52 +02:00
8b5b219a18
runtime: provide fixdfdi
2015-06-27 23:51:48 +02:00
3bd7f11737
update lwip
2015-06-27 22:48:41 +02:00
2d475e146b
runtime/flash_storage: use log not printf
2015-06-27 22:47:36 +02:00
87ea1433d3
dds: all working
2015-06-20 18:42:39 -06:00
5a9bdb2e33
DDS monitoring
2015-06-19 15:30:17 -06:00
03fe71228b
dds: phase computation fixes
2015-06-19 11:01:43 -06:00
Florent Kermarrec
449964cce8
runtime/mailbox: remove flush of L2 cache (L2 cache is now shared between CPUs)
2015-06-18 12:18:45 +02:00
b2af0f6cc3
soc,runtime: support TTL override
2015-06-09 19:51:02 +08:00
37c7ea31c3
gui: TTL override support
2015-06-06 00:03:30 +08:00
a2ae5e4706
runtime: report TTL status over UDP
2015-06-03 18:26:19 +08:00
59b339462c
Merge branch 'master' of github.com:m-labs/artiq
2015-06-02 17:45:16 +08:00
b81151eb42
soc: rtio monitor
2015-06-02 17:41:40 +08:00
Yann Sionneau
ed95038681
flash_storage: remove useless parentheses
2015-05-29 11:11:29 +02:00
Yann Sionneau
575dfade38
flash_storage comm: use OK/ERROR replies instead of specific FLASH_WRITE_REPLY
2015-05-29 11:10:40 +02:00
