M-Labs
/
artiq
mirror of https://github.com/m-labs/artiq.git
2
0
Fork 2
Code Issues Projects Releases Wiki Activity
7,853 Commits 13 Branches 35 Tags 25 MiB
Commit Graph

7853 Commits

Author SHA1 Message Date
Sebastien Bourdeauducq 977543e05a Merge branch 'master' into nac3 2021-11-03 21:37:18 +08:00
Robert Jördens 591507a7c0
Merge pull request #1774 from m-labs/fastino-cic 
Fastino cic
 2021-10-28 17:44:20 +02:00
Robert Jördens 5a5b0cc7c0 fastino: expand docs 2021-10-28 15:19:48 +00:00
Spaqin 69cddc6b86
rtio_clocking: add warnings for unsupported rtio_clock settings (#1773) 2021-10-28 16:34:22 +08:00
Spaqin 9b1d7e297d
runtime: clock input specification improvements 
closes #1735
 2021-10-28 16:21:51 +08:00
Harry Ho 21b07dc667 flake: fix missing freetype & fontconfig libs for Vivado GUI mode 2021-10-28 14:39:47 +08:00
Robert Jördens 1ff474893d Revert "fastino: make driver filter order configurable" 
This reverts commit 10c37b87ec.
 2021-10-28 06:29:56 +00:00
Robert Jördens 10c37b87ec fastino: make driver filter order configurable 2021-10-27 20:24:58 +00:00
Harry Ho c940f104f1 artiq_flash: fix gateware header not in little-endian for RISC-V 2021-10-25 11:20:26 +08:00
Harry Ho 0aa8a739aa sayma_rtm: fix RTM firmware not in little-endian for RISC-V 2021-10-25 11:20:26 +08:00
Sebastien Bourdeauducq 43eab14f56 flake: update dependencies 2021-10-21 15:06:38 +08:00
Sebastien Bourdeauducq cc15a4f572 flake: update Vivado 2021-10-21 11:24:55 +08:00
Sebastien Bourdeauducq df6aeb99f6 flake: check gateware timing 2021-10-18 11:09:10 +08:00
Sebastien Bourdeauducq bb61f2dae6 flake: update dependencies 2021-10-18 10:38:28 +08:00
Sebastien Bourdeauducq b0cbad530b flake: update dependencies 2021-10-16 19:10:28 +08:00
Sebastien Bourdeauducq 92cdfac35a flake: fix cargoDeps sha256 2021-10-16 18:20:25 +08:00
occheung bf180c168c flake.lock: update dependencies 2021-10-16 17:42:24 +08:00
occheung d5fa3d131a cargo.lock: update libc version for libfringe 2021-10-16 17:42:24 +08:00
occheung 6d3164a912 riscv: print mtval on panic 2021-10-16 17:42:24 +08:00
occheung 46326716fd runtime: bump libfringe, impl ecall abi 
See libfringe PR: M-Labs/libfringe#1
 2021-10-16 17:42:24 +08:00
occheung 0a59c889de satman/kern: init locked PMP on startup 2021-10-16 17:42:24 +08:00
occheung 27a7a96626 runtime: setup pmp + transfer to user 2021-10-16 17:42:24 +08:00
occheung a0bf11b465 riscv: impl pmp 2021-10-16 17:42:24 +08:00
occheung 790a20edf6 linker: generate stack guard + symbol 2021-10-16 17:42:24 +08:00
fanmingyu212 178a86bcda master: add an argument to set an experiment subdirectory 
Signed-off-by: Mingyu Fan <mingyufan@ucsb.edu>
 2021-10-15 16:54:31 +08:00
Sebastien Bourdeauducq fbd5c70250 Revert "runtime: expose rint from libm" 
Consistency with NAR3/Zynq where rint is not available.

This reverts commit f5100702f6.
 2021-10-11 08:12:58 +08:00
Sebastien Bourdeauducq 35d21c98d3 Revert "runtime: expose rint from libm" 
Consistency with NAR3/Zynq where rint is not available.

This reverts commit f5100702f6.
 2021-10-11 08:12:04 +08:00
Sebastien Bourdeauducq 17c283d091 runtime: expose rint from libm 2021-10-10 20:40:56 +08:00
Sebastien Bourdeauducq f5100702f6 runtime: expose rint from libm 2021-10-10 20:40:17 +08:00
Sebastien Bourdeauducq 3c1cbf47d2 phaser: add more slack during init. Closes #1757 2021-10-10 16:18:55 +08:00
Robert Jördens 3f6bf33298 fastino: add interpolator support 2021-10-08 15:47:07 +00:00
Harry Ho 501eb1fa23 flake: add microscope 2021-10-08 12:39:35 +08:00
Harry Ho ea9bc04407 flake: add jesd204b 2021-10-08 12:39:35 +08:00
Sebastien Bourdeauducq 97909d7619 remove old compiler, add nac3 dependency (WIP) 2021-10-08 00:30:27 +08:00
occheung 59065c4663 alloc_list: support alloc w/ large align 
Signed-off-by: Oi Chee Cheung <dc@m-labs.hk>
 2021-10-07 12:38:03 +08:00
Spaqin 1894f0f626
gateware: share RTIOClockMultiplier and fix_serdes_timing_path (#1760) 2021-10-07 08:19:38 +08:00
Sebastien Bourdeauducq 4bfd010f03 setup: Python 3.7+ 2021-09-27 17:46:25 +08:00
Etienne Wodey a8333053c9 sinara_tester: add device_db and test selection CLI options 
Signed-off-by: Etienne Wodey <etienne.wodey@aqt.eu>
 2021-09-27 17:44:50 +08:00
occheung 7a7e17f7e3 openocd: update and apply 4-byte address support patch 
See the relevant commit made in nix-scripts repo.
575ef05cd5
 2021-09-27 09:34:46 +08:00
Sebastien Bourdeauducq 3ed10221d8 compiler: remove big-endian support. Closes #1590 2021-09-13 13:40:24 +08:00
Sebastien Bourdeauducq e8a7a8f41e compiler: work around idiotic windoze behavior that causes conda ld.lld not to be found 2021-09-13 10:40:54 +08:00
Sebastien Bourdeauducq 4834966798 flake: add jsonschema to dev environment 2021-09-13 07:39:15 +08:00
Sebastien Bourdeauducq 7209e6f279 flake: add cargo-xbuild to dev environment 2021-09-13 07:20:36 +08:00
Sebastien Bourdeauducq ffb1e3ec2d wavesynth: np.int is deprecated 2021-09-13 07:02:35 +08:00
Sebastien Bourdeauducq 2d79d824f9 firmware: remove minor or1k leftovers 2021-09-12 20:03:37 +08:00
Sebastien Bourdeauducq 1a0c4219ec doc: mor1kx -> VexRiscv 2021-09-12 19:27:00 +08:00
Sebastien Bourdeauducq 2e5c32878f flake: add other KC705 NIST builds 2021-09-10 17:19:32 +08:00
occheung a573dcf3f9 board_misoc/build: use rv32 as target arg 
The original rv64 argument was only to match the misoc counterpart.
 2021-09-10 14:11:23 +08:00
occheung 448974fe11 runtime/main: cleanup 2021-09-10 13:59:53 +08:00
occheung b091d8cb66 kernel: flush cache before mod_init 
This could be necessary as redirecting instructions from D$ directly to I$ as it seems.
Related: https://github.com/SpinalHDL/VexRiscv/issues/137
 2021-09-10 13:25:12 +08:00