* master: (23 commits)
RELEASE_NOTES: update
pipistrello: add some inputs
Remove last vestiges of nist_qc1.
Fully drop AD9858 and kc705-nist_qc1 support (closes#576).
coredevice.dds: reimplement fully in ARTIQ Python.
compiler: unbreak casts to int32/int64.
analyses.constness: fix false positive on x[...].
inferencer: significantly improve the op-assignment diagnostic.
Fix tests.
Move mu_to_seconds, seconds_to_mu to Core.
artiq_devtool: don't crash on invalid utf-8.
artiq_devtool: detect a race condition during connect.
llvm_ir_generator: handle no-op coercions.
conda: use development version of migen/misoc
Revert accidentally committed code.
Revert "gateware: increase RTIO FIFO sizes for NIST_CLOCK. Closes#623"
analyses.invariant_detection: implement (#622).
Fix whitespace.
coredevice.dds: work around the round(numpy.float64()) snafu.
coredevice.dds: update from obsolete int(width=) syntax (fixes#621).
...
Before this commit, it displayed incorrect output if an error
appeared on 2nd run and beyond, and displayed messages for trying
to do "num32 -= num64" that made very little sense.
This is to support channels where variable length
event data is well-defined through zero-padding.
E.g. in the case of `Spline` zero-padding of events naturally
corresponds to low-order knots.
Use timestamp change as trigger. This assumes that writes to the
timestamp register always precede address and data writes.
It does not break support for ganged writes of the same event
timestamp and data/address to multiple channels or
channel-addresses.
