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https://github.com/m-labs/artiq.git
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runtime: support rtio data wider than 64 bit
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parent
342b9e977e
commit
641f07119f
@ -1,5 +1,5 @@
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from artiq.language.core import syscall
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from artiq.language.types import TInt64, TInt32, TNone
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from artiq.language.types import TInt64, TInt32, TNone, TList
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@syscall(flags={"nowrite"})
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@ -8,6 +8,12 @@ def rtio_output(time_mu: TInt64, channel: TInt32, addr: TInt32, data: TInt32
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raise NotImplementedError("syscall not simulated")
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@syscall(flags={"nowrite"})
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def rtio_output_list(time_mu: TInt64, channel: TInt32, addr: TInt32,
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data: TList(TInt32)) -> TNone:
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raise NotImplementedError("syscall not simulated")
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@syscall(flags={"nowrite"})
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def rtio_input_timestamp(timeout_mu: TInt64, channel: TInt32) -> TInt64:
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raise NotImplementedError("syscall not simulated")
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@ -58,7 +58,27 @@ void rtio_output(long long int timestamp, int channel, unsigned int addr,
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#ifdef CSR_RTIO_O_ADDRESS_ADDR
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rtio_o_address_write(addr);
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#endif
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rtio_o_data_write(data);
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MMPTR(CSR_RTIO_O_DATA_ADDR) = data;
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rtio_o_we_write(1);
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status = rtio_o_status_read();
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if(status)
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rtio_process_exceptional_status(timestamp, channel, status);
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}
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void rtio_output_list(long long int timestamp, int channel,
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unsigned int addr, struct artiq_list data)
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{
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int status, i;
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volatile unsigned int *p = &MMPTR(CSR_RTIO_O_DATA_ADDR);
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rtio_chan_sel_write(channel);
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rtio_o_timestamp_write(timestamp);
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#ifdef CSR_RTIO_O_ADDRESS_ADDR
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rtio_o_address_write(addr);
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#endif
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for(i=0;i<data.length;i++)
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*p++ = *data.elements++;
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rtio_o_we_write(1);
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status = rtio_o_status_read();
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if(status)
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@ -116,7 +136,7 @@ unsigned int rtio_input_data(int channel)
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}
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}
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data = rtio_i_data_read();
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data = MMPTR(CSR_RTIO_I_DATA_ADDR);
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rtio_i_re_write(1);
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return data;
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}
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@ -140,14 +160,14 @@ void rtio_log_va(long long int timestamp, const char *fmt, va_list args)
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word <<= 8;
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word |= *buf & 0xff;
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if(*buf == 0) {
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rtio_o_data_write(word);
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MMPTR(CSR_RTIO_O_DATA_ADDR) = word;
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rtio_o_we_write(1);
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break;
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}
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buf++;
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i++;
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if(i == 4) {
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rtio_o_data_write(word);
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MMPTR(CSR_RTIO_O_DATA_ADDR) = word;
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rtio_o_we_write(1);
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word = 0;
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i = 0;
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@ -11,12 +11,21 @@
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#define RTIO_I_STATUS_EMPTY 1
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#define RTIO_I_STATUS_OVERFLOW 2
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struct artiq_list {
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int32_t length;
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int32_t *elements;
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};
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void rtio_init(void);
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long long int rtio_get_counter(void);
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void rtio_log(long long int timestamp, const char *format, ...);
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void rtio_log_va(long long int timestamp, const char *format, va_list args);
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void rtio_output(long long int timestamp, int channel, unsigned int address,
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unsigned int data);
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void rtio_output_list(long long int timestamp, int channel,
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unsigned int addr, struct artiq_list data);
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/*
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* Waits at least until timeout and returns the timestamp of the first
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