M-Labs
/
artiq
mirror of https://github.com/m-labs/artiq.git
2
0
Fork 2
Code Issues Projects Releases Wiki Activity
5,401 Commits 13 Branches 35 Tags 25 MiB
Commit Graph

5401 Commits

Author SHA1 Message Date
Sebastien Bourdeauducq 0f4549655b sayma: use Xilinx RX synchronizer 
Cannot be used on Kasli, this breaks the bitstream entirely (nothing on UART).
 2018-02-19 17:49:53 +08:00
Sebastien Bourdeauducq 52049cf36a drtio: add Xilinx RX synchronizer 2018-02-19 17:49:43 +08:00
Sebastien Bourdeauducq 3bc575bee7 drtio: add missing define for Sayma master 2018-02-19 17:11:21 +08:00
Sebastien Bourdeauducq 7376ab0ff8 drtio: fix Sayma after 83abdd28 2018-02-19 17:10:55 +08:00
Florent Kermarrec f5831af535 drtio/transceiver/gtp_7series_init: don't reset gtp rx on power down 2018-02-19 10:03:19 +01:00
Florent Kermarrec 89a158c0c9 drtio/transceiver/gtp_7series_init: remove dead code 2018-02-19 10:02:23 +01:00
Florent Kermarrec 782051f474 drtio/transceiver/gtp_7series_init: add no retiming on gtp resets 2018-02-19 09:59:50 +01:00
Sebastien Bourdeauducq 01fa6c1c2e reorganize examples 2018-02-19 15:46:08 +08:00
Sebastien Bourdeauducq 4b4090518b drtio: clean up remnants of removed debug functions 2018-02-19 15:14:32 +08:00
Sebastien Bourdeauducq c329c83676 kasli: fix disable_si5324_ibuf no_retiming 2018-02-19 12:19:05 +08:00
Sebastien Bourdeauducq a93decdef2 kasli: disable DRTIO IBUFDS_GTE2 until Si5324 is initialized 2018-02-19 00:48:37 +08:00
Sebastien Bourdeauducq 94c20dfd4d drtio: fix misleading GenericRXSynchronizer comment 2018-02-19 00:47:54 +08:00
Sebastien Bourdeauducq 83abdd283a drtio: signal stable clock input to transceiver 2018-02-18 22:29:30 +08:00
Robert Jördens c87636ed2b si5324: fix cfb21ca 2018-02-18 11:38:20 +01:00
Robert Jördens caedcd5a15 ad9912: cleanup, document init() 2018-02-18 11:38:16 +01:00
Robert Jördens 75c89422c9 ad991[02]: sysclk can be 1 GHz 2018-02-18 10:29:19 +00:00
Sebastien Bourdeauducq 6ae1cc20aa conda: bump misoc (#908) 2018-02-18 12:35:49 +08:00
Sebastien Bourdeauducq 41adbef9a9 conda: bump misoc 2018-02-17 17:41:16 +08:00
Sebastien Bourdeauducq 287d533437 Revert "sayma_amc: remove RTM bitstream upload core. Closes #908" 
This reverts commit 2d4a1340ea.
 2018-02-17 17:38:48 +08:00
Sebastien Bourdeauducq 73985a9215 sayma: remove constraints at outputs of serwb PLL (see misoc d1489ed) 2018-02-17 17:38:17 +08:00
Sebastien Bourdeauducq 039dee4c8e si5324: rename SI5324_FREE_RUNNING to SI5324_AS_SYNTHESIZER 
The previous name was causing confusion with the FREE_RUN bit
that connects the crystal to CLKIN2.
 2018-02-17 13:54:50 +08:00
Sebastien Bourdeauducq cfb21ca126 si5324: fix usage of external CLKIN2 reference 2018-02-17 13:52:01 +08:00
Sebastien Bourdeauducq 07a31f8d86 conda: bump openocd 2018-02-17 13:21:10 +08:00
Sebastien Bourdeauducq fb8b36cd41 clean up ccc279b8 2018-02-17 12:10:46 +08:00
hartytp ccc279b8da rewrite HMC7043 init code without using ADI GUI outputs, working analog/digital delay 2018-02-17 12:07:11 +08:00
Robert Jördens e41f49cc75 kasli: opticlock 125 MHz, mark external reference case broken 2018-02-16 17:23:15 +00:00
Sebastien Bourdeauducq e4db84e214 doc: fix typo 2018-02-17 00:11:48 +08:00
Sebastien Bourdeauducq 7a5161d348 conda: bump misoc (#902) 2018-02-17 00:11:42 +08:00
Robert Jördens 0ef33dd0d8 manual: add note about the "correct" vivado version 
close #910
 2018-02-15 14:21:17 +01:00
Robert Jördens 7002bea0ab kasli: clean up urukul example more 2018-02-15 14:21:17 +01:00
Sebastien Bourdeauducq 4d42df2a7c kasli: set up Si5324 in standalone operation 2018-02-15 20:32:58 +08:00
Sebastien Bourdeauducq c5ae81f452 satman: remove unused 62.5MHz Si5324 settings 2018-02-15 20:29:51 +08:00
Sebastien Bourdeauducq d7387611c0 sayma: print RTM gateware version 2018-02-15 19:31:58 +08:00
whitequark d572c0c34d artiq_devtool: fix the hotswap action. 2018-02-14 23:10:27 +00:00
whitequark fe50018037 firmware: make network tracing runtime switchable. 2018-02-14 23:03:20 +00:00
Robert Jördens 2adba3ed33 urukul: document ad9912, and cpld, fix api 2018-02-14 09:45:17 +01:00
Robert Jördens ede98679fc ad9910: add documentation 2018-02-14 09:05:03 +01:00
Robert Jördens b6395a809b kasli: remove old urukul test code 2018-02-13 22:16:57 +01:00
Robert Jördens be693bc8a9 opticlock: examples 2018-02-13 22:13:40 +01:00
Robert Jördens a3d136d30d opticlock: wire urukul and novogorny 2018-02-13 22:13:40 +01:00
Robert Jördens 7f1bfddeda ad9910: tweak spi timing for higher speed 2018-02-13 22:13:40 +01:00
Robert Jördens 6a6695924f urukul: proto 8 2018-02-13 22:13:40 +01:00
Robert Jördens bc6af03a61 urukul: (proto 7) drop att_le 2018-02-13 22:13:40 +01:00
Sebastien Bourdeauducq df177bfd5b use new misoc identifier 2018-02-13 20:38:48 +08:00
Sebastien Bourdeauducq ab5f397fea sed/fifos: use AsyncFIFOBuffered 
(D)RTIO now passes timing at 150MHz on Kasli.
 2018-02-13 20:02:51 +08:00
Sebastien Bourdeauducq 00f42f912b rename 'RTM identifier' to 'RTM magic number' 
Avoids confusion with the MiSoC identifier (containing the ARTIQ version).
 2018-02-13 20:02:51 +08:00
Sebastien Bourdeauducq 96b948f57f remote_csr: add sanity check of CSR CSV type column 2018-02-13 20:02:51 +08:00
Sebastien Bourdeauducq e67a289e2b examples: add SAWG sines (DAC synchronization test) 2018-02-13 20:02:51 +08:00
Florent Kermarrec bfdda340fd drtio/transceiver/gtp_7series: use parameters from xilinx wizard 2018-02-13 00:23:59 +01:00
Florent Kermarrec 180c28551d drtio/gateware/transceiver/gtp_7series: add power down state before reset on rx (seems to make restart reliable) 2018-02-09 20:17:02 +01:00