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Commit Graph

100 Commits

Author SHA1 Message Date
f7232fd3d1 support exceptions raised by RPCs 2014-12-20 21:33:22 +08:00
0d10ae7580 rpc: support all data types as parameters 2014-12-19 12:46:24 +08:00
059608d1fd dds: fix phase modes 2014-12-09 13:50:33 +08:00
fc690ead75 runtime: support clock switching 2014-12-02 14:06:32 +08:00
94218f785e comm_serial: cleanup 2014-12-02 11:09:02 +08:00
Yann Sionneau
20adb57140 comm_serial: allow to use dynamic baudrate 2014-12-02 10:42:14 +08:00
c591f1a74d targets/ARTIQMiniSoC: support dynamic switching of RTIO clock to XTRIG 2014-12-01 18:53:29 +08:00
cd587e4f12 rtio: do housekeeping in gateware 2014-12-01 17:32:36 +08:00
99d530e498 targets/ARTIQMiniSoC: remove 2 TTL channels to make room in FPGA 2014-12-01 17:31:35 +08:00
50e0bf3280 rtio: optimize flag handling 2014-12-01 14:29:50 +08:00
572eecc57b rtio: stricter upper bound on guard time to avoid race condition 2014-12-01 14:27:03 +08:00
7166ca82d1 targets/ARTIQMiniSoC: map RTIO CSRs directly on Wishbone (reduces programming time by 30%) 2014-11-30 22:31:55 +08:00
1f6441948d more TTL channels and larger input FIFOs on Papilio Pro 2014-11-30 15:50:57 +08:00
e5286c57ab rtio: fix input FIFO depth config 2014-11-30 12:12:35 +08:00
bf745e53c9 rtio: register FIFO output to improve timing 2014-11-30 10:51:12 +08:00
dda4002ae1 rtio/phy: fix input synchronization 2014-11-30 10:50:48 +08:00
c78c5a2b4f rtio: fix guard cycle computation 2014-11-30 01:00:52 +08:00
39c4b5416f targets/ARTIQMiniSoC: 125MHz RTIO clocking 2014-11-30 01:00:27 +08:00
9aafe89518 rtio: use Record 2014-11-30 00:59:39 +08:00
901073acf3 asynchronous RTIO 2014-11-30 00:13:54 +08:00
44ec3eae3d soc/target: use minicon by default 2014-11-28 10:21:43 +08:00
65567e1201 soc/target: remap RTIO to avoid conflict with Ethernet MAC+PHY 2014-11-21 15:51:51 -08:00
dfd779c7c5 core: add underflow recovery function 2014-11-20 12:38:52 -08:00
1780759327 dds: phase control (mostly untested) 2014-11-20 12:32:56 -08:00
17f5a31320 runtime/dds: fix reset glitches 2014-11-15 11:23:23 -07:00
5105b88302 rtio: raise input overflow exception 2014-10-21 23:41:02 +08:00
9a14081031 rtio: add pileup count reporting 2014-10-21 23:14:01 +08:00
346cca9e90 soc/target: remap RTIO to avoid conflict with spiflash and ddrphy in MiSoC 2014-10-21 18:40:08 +08:00
61a50ee53c reorganize for devices/controllers 2014-10-19 23:51:49 +08:00
0c9632d71b runtime/exception_raise: never return 2014-10-15 16:11:28 +08:00
d22c30650d rtio: add timestamp function 2014-10-14 15:54:10 +08:00
7d48ef263a soc/runtime: fix RTIO sequence error detection on FUD 2014-10-14 12:47:04 +08:00
1c24a5971b rtio: error recovery 2014-10-10 20:12:22 +08:00
53b259b9a0 soc/runtime/dds: fix FUD sequence error detection 2014-10-05 10:34:32 +08:00
5d8c53abb3 soc/runtime/exceptions: do not crash when exception is raised with no handler 2014-10-05 10:33:27 +08:00
76fed11d59 rtio: raise RTIOSequenceError exceptions when events are not submitted in-order 2014-09-30 19:32:11 +08:00
e263b63527 soc/runtime: raise underflow exception for replace and DDS FUD operations 2014-09-26 17:24:45 +08:00
af0cd902d3 get frequency from RTIO, support fractional frequencies 2014-09-26 17:24:06 +08:00
f4d6bfc094 soc/runtime: raise exception on RTIO underflow 2014-09-25 12:55:50 +08:00
378ca64193 soc/runtime/exception: fix eid bug 2014-09-25 12:55:22 +08:00
538aaa4c14 rtio: fix o_error csr size 2014-09-25 12:54:26 +08:00
1b81fc8a8f soc/runtime: cleanup/simplify exception_longjmp 2014-09-24 00:00:10 +08:00
af15f45bb9 runtime: do not use buggy llvm.eh.sjlj.* intrinsics 2014-09-23 22:09:08 +08:00
0a02d9fb78 soc/runtime: add levels to exception_pop 2014-09-23 16:22:32 +08:00
ec7a92983d soc/runtime: provide exception handling services 2014-09-22 13:19:26 +08:00
b37ceb328f soc/runtime: fix use of setjmp 2014-09-22 13:18:48 +08:00
3de24619b2 corecom: exception support 2014-09-21 23:36:10 +08:00
0c9f05dc80 soc/runtime: add exception management functions 2014-09-21 23:32:14 +08:00
d52d641dcd soc/runtime/services: add alternative names for comparedf2 routines 2014-09-18 09:36:06 +08:00
f0f65ba3a7 soc/target: add optional test signal generator 2014-09-17 19:53:55 +08:00