Spaqin
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17efc28dbe
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DRTIO: RTIO/SYS clock merge
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2022-12-17 15:39:54 +08:00 |
occheung
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c6e0e26440
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drtio: accept 32b/64b bus
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2021-11-08 16:59:08 +08:00 |
Sebastien Bourdeauducq
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87e0384e97
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drtio: separate aux controller
This helps with managing CSR groups and heterogeneous (satellite/repeaters) DRTIO cores.
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2018-09-05 17:56:58 +08:00 |
Sebastien Bourdeauducq
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1e47e638bb
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drtio: implement inputs in RTPacketSatellite, reorganize code
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2017-03-07 00:46:59 +08:00 |
Sebastien Bourdeauducq
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e9592105ce
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drtio: fix aux controller clock domain mistakes
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2016-12-14 10:16:45 +08:00 |
Sebastien Bourdeauducq
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e532261a9b
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drtio: fix FullMemoryWE usage
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2016-11-23 12:25:43 +08:00 |
Sebastien Bourdeauducq
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140bb0ecee
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drtio: aux controller fixes
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2016-11-16 19:44:03 +08:00 |
Sebastien Bourdeauducq
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6c9965b444
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drtio: aux controller fixes
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2016-11-15 12:02:41 +08:00 |
Sebastien Bourdeauducq
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e1394db861
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drtio: aux controller minor fixes
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2016-11-14 17:26:30 +08:00 |
Sebastien Bourdeauducq
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a4d92716da
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drtio: fix aux receiver, add aux transmitter
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2016-11-14 17:18:54 +08:00 |
Sebastien Bourdeauducq
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f2f131e0fb
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drtio: add aux receiver (untested)
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2016-11-14 00:04:53 +08:00 |