07d43b6e5f
wrpll: babysit Vivado DSP retiming
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Design now passes timing.
2020-10-08 17:51:27 +08:00
7dfb4af682
kasli2: work around vivado clock constraint problem
2020-10-08 16:31:39 +08:00
96a5df0dc6
kasli2: add false path constraint for wrpll helper clock
2020-10-08 16:19:44 +08:00
6248970ef8
wrpll: clean up matlab comparison test
2020-10-08 15:40:15 +08:00
hartytp
cd8c2ce713
wrpll: add test to compare collector+filter against Matlab simulation
2020-10-08 15:36:56 +08:00
hartytp
d780faf4ac
wrpll.si549: initialize the clock divider to a sensible value
2020-10-08 15:32:27 +08:00
hartytp
e6ff2ddc32
wrpll: add more diagnostics in firmware and adapt to recent gateware changes
2020-10-08 15:32:27 +08:00
hartytp
7d7be6e711
wrpll.core: move collector into helper CD so we can get tags out while the filters are reset
2020-10-08 15:32:27 +08:00
3fa5d0b963
wrpll: clean up sign extension
2020-10-08 15:32:27 +08:00
hartytp
87911810d6
wrpll.core: add CSRs to monitor the collector outputs
2020-10-08 15:32:27 +08:00
hartytp
f2f942a8b4
wrpll.ddmtd: remove CSRs from DDMTD
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We will gather then from the collector output so we can get all tags on the same cycle
2020-10-08 15:32:27 +08:00
hartytp
85bb641917
wrpll.ddmtd: fix first edge deglitcher
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The blind counter should be held in reset whenever the input is high,
not just when there is a rising edge (otherwise the counter runs down
during the main pulse and can then re-trigger on jitter from the falling edge)
2020-10-08 15:32:27 +08:00
hartytp
f3cd0fc675
wrpll.filters: the helper clipping threshold is currently way too low. Move clipping after the bitshift to increase a bit.
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TODO: think about this and pick a sensible threshold (and also think about integrator anti windup)
2020-10-08 15:32:27 +08:00
hartytp
e5e648bde1
wrpll: add bit shift for collector helper output
2020-10-08 15:32:27 +08:00
hartytp
c9ae406ac6
wrpll: change the DDMTD helper frequency to match CERN, improve docs
2020-10-08 15:32:27 +08:00
hartytp
f6f6045f1a
wrpll.thls: fix make
2020-10-08 15:32:27 +08:00
hartytp
b44b870452
wrpll.filters: update to match Weida's MatLab simulations
2020-10-08 15:32:27 +08:00
hartytp
e9ab434fa7
wrpll.core: update for modified collector
2020-10-08 15:32:27 +08:00
17c952b8fb
wrpll: style
2020-10-08 15:32:27 +08:00
hartytp
ebb7ccbfd1
wrpll: document DDMTD collector and fix unwrapping
2020-10-08 15:32:27 +08:00
7c2519c912
manual: nixpkgs 20.09
2020-10-08 09:18:46 +08:00
1bfe977203
manual: sphinx mock module whack-a-mole
2020-10-07 19:25:26 +08:00
66401aee9c
dashboard: cleanup import
2020-10-07 19:24:54 +08:00
6baf3b2198
RELEASE_NOTES: fix indentation
2020-10-07 19:24:34 +08:00
fe6115bcbb
compiler: fix incorrect with behavior
2020-10-07 18:59:35 +08:00
02f46e8b79
Fixes none to bool coercion
...
Fixes #1413 and #1414 .
2020-10-07 15:34:24 +08:00
88d346fa26
fixes with statement with multiple items
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Closes #1478
2020-10-07 15:33:34 +08:00
9214e0f3e2
firmware: fix Si5324 CKIN selection on Kasli 2.0
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https://github.com/sinara-hw/Kasli/issues/82#issuecomment-702129805
2020-10-02 20:35:32 +08:00
a65239957f
ad53xx: distinguish errors
2020-09-24 10:52:03 +02:00
c55f2222dc
fastino: documentation and eem pass-through
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* Repeat information about matching log2_width a few times
in the hope that people read it. #1518
* Pass through log2_width in kasli_generic json. close #1481
* Check DAC value range. #1518
2020-09-22 17:58:53 +02:00
29c940f4e3
kasli2: forward sma_clkin to si5324
2020-09-17 16:53:43 +08:00
bff611a888
test: relax test_dma_playback_time on Zynq
2020-09-11 11:21:45 +08:00
6195b1d3a0
rpc: fixed _write_bool
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Closes #1519
2020-09-04 13:49:22 +08:00
56aa22caeb
fastino: document/cleanup
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* added documentation on `update`/`hold` mechanism
* mask machine unit values
* cleanup coredevice driver
close #1518
2020-09-03 17:44:26 +02:00
1b475bdac4
build_soc: remove assertion that was used for test runs
2020-09-03 20:24:18 +08:00
458a411320
metlino_sayma_ttl: Fix RTIO frequency & demo code ( #1516 )
2020-09-03 15:08:31 +08:00
47e88dfcbe
Revert "test: temporarily disable test_async_throughput"
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This reverts commit f0289d49ab
2020-09-03 14:19:55 +08:00
002a71dd8d
build_soc: rename identifier_str to gateware_identifier_str
2020-09-02 00:00:57 +08:00
4398a2d5fa
test: relax loopback gate timing
2020-09-01 17:50:09 +08:00
f0289d49ab
test: temporarily disable test_async_throughput
...
M-Labs/artiq-zynq#104
2020-09-01 17:49:40 +08:00
8d5dc0ad2a
test: relax test_pulse_rate on Zynq
2020-09-01 17:08:26 +08:00
f294d039b3
test: skip NonexistentI2CBus if I2C is not supported
2020-09-01 16:47:04 +08:00
91df3d7290
build_soc: override identifier_str only for gateware
2020-09-01 10:46:39 +08:00
3d84135810
examples: add Metlino master, Sayma satellite with TTLOuts via FMC
2020-08-31 16:21:45 +08:00
dfbf3311cb
sayma_amc: add support for 4x DIO output channels via FMC
2020-08-31 16:21:45 +08:00
1ad9deaf91
fmcdio_vhdci_eem: fix pin naming
2020-08-31 16:21:45 +08:00
45ae6202c0
build_soc: add identifier_str override option
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Signed-off-by: Stephan Maka <stephan@spaceboyz.net>
2020-08-31 11:48:58 +08:00
b2572003ac
RPC: optimization by caching
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This reduced the calls needed for socket send/recv.
2020-08-28 14:58:34 +08:00
69f0699ebd
test: improved test_performance
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1. Added tests for small payload.
2. Added statistics.
2020-08-28 14:58:34 +08:00
7cf974a6a7
comm_kernel: fix typo
2020-08-28 12:25:23 +08:00
