artiq

Author	SHA1	Message	Date
Marius Weber	4fa2028671	phaser: fix coarse mixer register offset The CMIX bits are bits 12-15 in register 0x0d. This has been checked against the datasheet and verified on hardware. Until now, the bit for CMIX1 was written to CMIX0. The CMIX0 bit was written to a reserved bit. Signed-off-by: Marius Weber <marius.weber@physics.ox.ac.uk>	2021-05-08 14:48:47 +01:00
Marius Weber	75445fe5f0	Phaser: expose and automate clearing of DAC `sif_sync` (close #1630 and #1650 ) `sif_sync` must be triggered to apply NCO frequency changes. To achieve per channel frequency tunability exeeding the range of the DUC, the NCO frequeny must adjusted. User code will need to trigger `sif_sync` to achieve this. `sif_sync` can only be triggered if the bit was cleared. To avoid this pitfall, the clearing of `sif_sync` is automated. Signed-off-by: Marius Weber <marius.weber@physics.ox.ac.uk>	2021-05-08 14:48:47 +01:00
Marius Weber	c7e992e26d	Phaser: flake8 Signed-off-by: Marius Weber <marius.weber@physics.ox.ac.uk>	2021-05-08 14:48:46 +01:00
Robert Jördens	03d5f985f8	phaser: another artiq-python signed integer quirk	2020-09-23 15:40:54 +00:00
Robert Jördens	ef65ee18bd	dac34h84: unflip spectrum, clear nco	2020-09-23 08:35:56 +00:00
Robert Jördens	85d16e3e5f	phaser: tweaks	2020-09-22 15:27:38 +00:00
Robert Jördens	fd5e221898	phaser: dac and trf register maps, init code	2020-09-22 14:08:39 +00:00