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phaser: tweaks
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@ -32,7 +32,7 @@ class DAC34H84:
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revbus = 0
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twos = 1
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coarse_dac = 0xa # 20.6 mA, 0-15
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coarse_dac = 9 # 18.75 mA, 0-15
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sif_txenable = 0
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mask_alarm_from_zerochk = 0
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@ -119,6 +119,7 @@ class Phaser:
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:param core_device: Core device name (default: "core")
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:param miso_delay: Fastlink MISO signal delay to account for cable
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and buffer round trip. Tuning this might be automated later.
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:param clk_sel: Select the external SMA clock input (1 or 0)
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:param dac: DAC34H84 DAC settings as a dictionary.
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:param trf0: Channel 0 TRF372017 quadrature upconverter settings as a
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dictionary.
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@ -134,8 +135,8 @@ class Phaser:
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kernel_invariants = {"core", "channel_base", "t_frame", "miso_delay",
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"dac_mmap"}
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def __init__(self, dmgr, channel_base, miso_delay=1, core_device="core",
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dac=None, trf0=None, trf1=None):
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def __init__(self, dmgr, channel_base, miso_delay=1, clk_sel=0,
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dac=None, trf0=None, trf1=None, core_device="core"):
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self.channel_base = channel_base
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self.core = dmgr.get(core_device)
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# TODO: auto-align miso-delay in phy
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@ -144,6 +145,7 @@ class Phaser:
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# self.core.seconds_to_mu(10*8*4*ns) # unfortunately this returns 319
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assert self.core.ref_period == 1*ns
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self.t_frame = 10*8*4
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self.clk_sel = clk_sel
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self.dac_mmap = DAC34H84(dac).get_mmap()
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@ -151,14 +153,13 @@ class Phaser:
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for ch, trf in enumerate([trf0, trf1])]
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@kernel
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def init(self, clk_sel=0):
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def init(self):
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"""Initialize the board.
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Verifies board and chip presence, resets components, performs
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communication and configuration tests and establishes initial
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conditions.
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:param clk_sel: Select the external SMA clock input (1 or 0)
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"""
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board_id = self.read8(PHASER_ADDR_BOARD_ID)
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if board_id != PHASER_BOARD_ID:
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@ -167,7 +168,7 @@ class Phaser:
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hw_rev = self.read8(PHASER_ADDR_HW_REV)
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delay(.1*ms) # slack
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has_upconverter = hw_rev & PHASER_HW_REV_VARIANT
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is_baseband = hw_rev & PHASER_HW_REV_VARIANT
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gw_rev = self.read8(PHASER_ADDR_GW_REV)
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delay(.1*ms) # slack
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@ -183,7 +184,7 @@ class Phaser:
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self.set_leds(0x00)
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self.set_fan_mu(0)
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# bring everything out of reset, keep tx off
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self.set_cfg(clk_sel=clk_sel, dac_txena=0)
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self.set_cfg(clk_sel=self.clk_sel, dac_txena=0)
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# TODO: crossing dac_clk (125 MHz) edges with sync_dly (0-7 ns)
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# should change the optimal fifo_offset by 4
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@ -269,7 +270,7 @@ class Phaser:
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abs(data_i - data_q) > 2):
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raise ValueError("DUC+oscillator phase/amplitude test failed")
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if has_upconverter:
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if not is_baseband:
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for data in channel.trf_mmap:
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channel.trf_write(data)
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delay(.1*ms)
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@ -279,7 +280,7 @@ class Phaser:
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if not lock_detect:
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raise ValueError("TRF quadrature upconverter lock failure")
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self.set_cfg(clk_sel=clk_sel) # txena
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self.set_cfg(clk_sel=self.clk_sel) # txena
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@kernel
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def write8(self, addr, data):
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@ -12,7 +12,7 @@ class TRF372017:
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cal_clk_sel = 12 # /16, 4b
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ndiv = 420 # 16b
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pll_div_sel = 0b01 # /1, 2b
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pll_div_sel = 0 # /1, 2b
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prsc_sel = 1 # 8/9
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vco_sel = 2 # 2b
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vcosel_mode = 0
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@ -106,7 +106,7 @@ class TRF372017:
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(self.en_extvco << 17) | (self.en_isource << 18) |
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(self.ld_ana_prec << 19) | (self.cp_tristate << 21) |
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(self.speedup << 23) | (self.ld_dig_prec << 24) |
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(self.en_dith << 25) | (self.mod_ord << 27) |
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(self.en_dith << 25) | (self.mod_ord << 26) |
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(self.dith_sel << 28) | (self.del_sd_clk << 29) |
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(self.en_frac << 31))
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mmap.append(
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