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phaser: fix coarse mixer register offset 

The CMIX bits are bits 12-15 in register 0x0d. This has been checked
against the datasheet and verified on hardware. Until now, the bit for
CMIX1 was written to CMIX0. The CMIX0 bit was written to a reserved bit.

Signed-off-by: Marius Weber <marius.weber@physics.ox.ac.uk>
pull/1657/head
Marius Weber 2021-04-06 17:34:28 +01:00
parent 515cfa7dfb
commit 4fa2028671
1 changed files with 1 additions and 1 deletions
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2
artiq/coredevice/dac34h84.py
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@ -201,7 +201,7 @@ class DAC34H84:
mmap.append(
(0x0d << 16) |
(self.cmix_fs8 << 15) | (self.cmix_fs4 << 14) |
(self.cmix_fs2 << 12) | (self.cmix_nfs4 << 11) |
(self.cmix_fs2 << 13) | (self.cmix_nfs4 << 12) |
(self.qmc_gainb << 0))
mmap.append((0x0e << 16) | (self.qmc_gainc << 0))
mmap.append(