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artiq
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Phaser: flake8 

Signed-off-by: Marius Weber <marius.weber@physics.ox.ac.uk>
pull/1657/head
Marius Weber 2021-04-02 11:16:14 +01:00
parent eb38b664e3
commit c7e992e26d
3 changed files with 9 additions and 5 deletions
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3
artiq/coredevice/dac34h84.py
View File

@ -178,7 +178,8 @@ class DAC34H84:
(self.collisiongone_ena << 12) | (self.sif4_ena << 7) |
(self.mixer_ena << 6) | (self.mixer_gain << 5) |
(self.nco_ena << 4) | (self.revbus << 3) | (self.twos << 1))
mmap.append((0x03 << 16) | (self.coarse_dac << 12) | (self.sif_txenable << 0))
mmap.append((0x03 << 16) | (self.coarse_dac << 12) |
(self.sif_txenable << 0))
mmap.append(
(0x07 << 16) |
(self.mask_alarm_from_zerochk << 15) | (1 << 14) |

4
artiq/coredevice/phaser.py
View File

@ -1,6 +1,8 @@
from numpy import int32, int64
from artiq.language.core import kernel, delay_mu, delay
from artiq.coredevice.rtio import rtio_output, rtio_input_data
from artiq.language.units import us, ns, ms, MHz, dB
from artiq.language.units import us, ns, ms, MHz
from artiq.language.types import TInt32
from artiq.coredevice.dac34h84 import DAC34H84
from artiq.coredevice.trf372017 import TRF372017

7
artiq/coredevice/trf372017.py
View File

@ -92,9 +92,10 @@ class TRF372017:
(self.cal_clk_sel << 27))
mmap.append(
0xa |
(self.ndiv << 5) | (self.pll_div_sel << 21) | (self.prsc_sel << 23) |
(self.vco_sel << 26) | (self.vcosel_mode << 28) |
(self.cal_acc << 29) | (self.en_cal << 31))
(self.ndiv << 5) | (self.pll_div_sel << 21) |
(self.prsc_sel << 23) | (self.vco_sel << 26) |
(self.vcosel_mode << 28) | (self.cal_acc << 29) |
(self.en_cal << 31))
mmap.append(0xb | (self.nfrac << 5))
mmap.append(
0xc |