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phaser: another artiq-python signed integer quirk

This commit is contained in:
Robert Jördens 2020-09-23 15:40:54 +00:00
parent ef65ee18bd
commit 03d5f985f8
2 changed files with 8 additions and 7 deletions
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9
artiq/coredevice/dac34h84.py
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@ -121,10 +121,11 @@ class DAC34H84:
path_c_sel = 2
path_d_sel = 3
# swap dac pairs (CDAB) for layout
dac_a_sel = 2
dac_b_sel = 3
dac_c_sel = 0
dac_d_sel = 1
# swap I-Q dacs for spectral inversion
dac_a_sel = 3
dac_b_sel = 2
dac_c_sel = 1
dac_d_sel = 0
dac_sleep_en = 0b1111 # msb a
clkrecv_sleep_en = 1

6
artiq/coredevice/phaser.py
View File

@ -651,7 +651,7 @@ class PhaserChannel:
:param frequency: DUC frequency in Hz (passband from -200 MHz to
200 MHz, wrapping around at +- 250 MHz)
"""
ftw = int32(round(frequency*((1 << 31)/(250*MHz))))
ftw = int32(round(frequency*((1 << 30)/(125*MHz))))
self.set_duc_frequency_mu(ftw)
@kernel
@ -689,7 +689,7 @@ class PhaserChannel:
:param frequency: NCO frequency in Hz (passband from -400 MHz
to 400 MHz, wrapping around at +- 500 MHz)
"""
ftw = int32(round(frequency*((1 << 31)/(500*MHz))))
ftw = int32(round(frequency*((1 << 30)/(250*MHz))))
self.set_nco_frequency_mu(ftw)
@kernel
@ -831,7 +831,7 @@ class PhaserOscillator:
:param frequency: Frequency in Hz (passband from -10 MHz to 10 MHz,
wrapping around at +- 12.5 MHz)
"""
ftw = int32(round(frequency*((1 << 31)/(12.5*MHz))))
ftw = int32(round(frequency*((1 << 30)/(6.25*MHz))))
self.set_frequency_mu(ftw)
@kernel