Commit Graph

20 Commits (afe3c165da4af89a9162090567e7e8c30ba1abcd)

Author SHA1 Message Date
mwojcik afe3c165da moved 3.3v signals to one place, removed duplicate 2021-10-13 16:14:09 +08:00
mwojcik bbb8c59ade replaced sma gpio with pmod1_0 2021-10-13 16:04:40 +08:00
mwojcik 285b034a6b Merge branch 'master' into 117_rtio_channels 2021-10-13 13:09:59 +08:00
mwojcik d04a7decfe removed simple variants from zc706 2021-10-08 11:07:12 +02:00
mwojcik 866e01fff3 Merge branch 'master' into 117_rtio_channels 2021-10-08 10:30:41 +02:00
mwojcik ab0c205dd2 gateware: add DRTIO
Reviewed-on: #140
Co-authored-by: mwojcik <mw@m-labs.hk>
Co-committed-by: mwojcik <mw@m-labs.hk>
2021-10-08 16:12:30 +08:00
mwojcik a20598da78 verified missing pins in zc706 docs, added ams, sd 2021-10-06 15:32:17 +02:00
mwojcik 0f0f0f8986 rearranged rtio for nist qc2 2021-10-06 15:01:22 +02:00
mwojcik ab3ac79655 zc706 nist clock: started rtio channel changes 2021-10-05 15:50:16 +02:00
Sebastien Bourdeauducq 18e05c91e1 zc706: si5324 is not needed for standalone target 2021-08-04 09:14:19 +08:00
mwojcik e3d3cb2311 si5324: bring on par with mainline ARTIQ (#132)
si5324 driver in runtime should be now equal in function to the one in artiq.

kasli-soc has no way of doing a hard reset on the peripheral, but zc706 does.

Reviewed-on: #132
Co-authored-by: mwojcik <mw@m-labs.hk>
Co-committed-by: mwojcik <mw@m-labs.hk>
2021-08-04 09:12:38 +08:00
Sebastien Bourdeauducq 506c741238 support absence of gateware RTIO clock selection mux
Hydra zc706-hitl-tests Hydra build #130237 of artiq:zynq:zc706-hitl-tests Details
2021-02-15 21:41:30 +08:00
Sebastien Bourdeauducq 1e20259c36 fix acpki selection 2020-08-04 13:26:45 +08:00
Sebastien Bourdeauducq f8d4036451 add ACP kernel initiator
Based on work by Chris Ballance
https://github.com/m-labs/artiq/issues/1167#issuecomment-427188287
#55

Work-in-progress, only gateware part and build system, untested.
2020-08-04 13:15:26 +08:00
Sebastien Bourdeauducq 523524c319 zc706: add RTIO log channels 2020-07-19 14:05:35 +08:00
Sebastien Bourdeauducq f69e41af5e gateware: fix VADJ I/O standard conflict 2020-07-16 17:58:31 +08:00
Sebastien Bourdeauducq 6a361893c2 gateware: make LEDs common to all variants
Makes quick testing easier.
2020-07-16 17:36:27 +08:00
Sebastien Bourdeauducq 8e758ecc17 add RTIO analyzer core (untested) 2020-07-15 23:06:34 +08:00
Sebastien Bourdeauducq a7073edf79 add DMA core (untested) 2020-07-13 10:37:17 +08:00
Sebastien Bourdeauducq e3ff21b1b5 create gateware folder 2020-07-11 17:49:54 +08:00