Merge branch 'master' into 117_rtio_channels

pull/148/head
mwojcik 1 year ago
commit 285b034a6b
  1. 8
      README.md
  2. 18
      default.nix
  3. 14
      src/Makefile
  4. 39
      src/gateware/zc706.py

@ -45,7 +45,7 @@ Note: if you are using Nix channels the first time, you need to be aware of this
Pure build with Nix and execution on a remote JTAG server:
```shell
nix-build -A zc706-simple-jtag # or zc706-nist_qc2-jtag or zc706-nist_clock-jtag
nix-build -A zc706-nist_clock-jtag # or zc706-nist_qc2-jtag or zc706-nist_clock_satellite-jtag etc.
./remote_run.sh
```
@ -54,8 +54,8 @@ Impure incremental build and execution on a remote JTAG server:
```shell
nix-shell
cd src
gateware/zc706.py -g ../build/gateware # build gateware
make # build firmware
gateware/zc706.py -g ../build/gateware -v <variant> # build gateware
make GWARGS="-v <variant>" <runtime/satman> # build firmware
cd ..
./remote_run.sh -i
```
@ -64,6 +64,8 @@ Notes:
- This is developed with Nixpkgs 21.05, and the ``nixbld.m-labs.hk`` binary substituter can also be used here (see the ARTIQ manual for the public key and instructions).
- The impure build process is also compatible with non-Nix systems.
- When calling make, you need to specify both the variant and firmware type.
- Firmware type must be either ``runtime`` for DRTIO-less or DRTIO master variants, or ``satman`` for DRTIO satellite.
- If the board is connected to the local machine, use the ``local_run.sh`` script.
- To update ``zynq-rs``, update the cargo files as per usual for Rust projects, but also keep ``zynq-rs.nix`` in sync.

@ -8,7 +8,7 @@ let
vivado = import <artiq-fast/vivado.nix> { inherit pkgs; };
# FSBL configuration supplied by Vivado 2020.1 for these boards:
fsblTargets = ["zc702" "zc706" "zed"];
sat_variants = ["satellite" "acpki_satellite" "nist_clock_satellite" "nist_qc2_satellite"];
sat_variants = ["satellite" "nist_clock_satellite" "nist_qc2_satellite" "acpki_nist_clock_satellite" "acpki_nist_qc2_satellite"];
build = { target, variant, json ? null }: let
szl = (import zynq-rs)."${target}-szl";
fsbl = import "${zynq-rs}/nix/fsbl.nix" {
@ -35,7 +35,7 @@ let
export XARGO_RUST_SRC="${rustPlatform.rust.rustc}/lib/rustlib/src/rust/library"
export CLANG_EXTRA_INCLUDE_DIR="${pkgs.llvmPackages_9.clang-unwrapped.lib}/lib/clang/9.0.1/include"
export CARGO_HOME=$(mktemp -d cargo-home.XXX)
make TARGET=${target} GWARGS="${if json == null then "-V ${variant}" else json}" ../build/${fwtype}.bin
make TARGET=${target} GWARGS="${if json == null then "-V ${variant}" else json}" ${fwtype}
'';
installPhase = ''
@ -81,14 +81,14 @@ let
bifdir=`mktemp -d`
cd $bifdir
ln -s ${szl}/szl.elf szl.elf
ln -s ${firmware}/runtime.elf runtime.elf
ln -s ${firmware}/${fwtype}.elf ${fwtype}.elf
ln -s ${gateware}/top.bit top.bit
cat > boot.bif << EOF
the_ROM_image:
{
[bootloader]szl.elf
top.bit
runtime.elf
${fwtype}.elf
}
EOF
mkdir $out $out/nix-support
@ -106,13 +106,13 @@ let
cd $bifdir
ln -s ${fsbl}/fsbl.elf fsbl.elf
ln -s ${gateware}/top.bit top.bit
ln -s ${firmware}/runtime.elf runtime.elf
ln -s ${firmware}/${fwtype}.elf ${fwtype}.elf
cat > boot.bif << EOF
the_ROM_image:
{
[bootloader]fsbl.elf
top.bit
runtime.elf
${fwtype}.elf
}
EOF
mkdir $out $out/nix-support
@ -133,18 +133,12 @@ let
);
in
(
(build { target = "zc706"; variant = "simple"; }) //
(build { target = "zc706"; variant = "master"; }) //
(build { target = "zc706"; variant = "satellite"; }) //
(build { target = "zc706"; variant = "nist_clock"; }) //
(build { target = "zc706"; variant = "nist_clock_master"; }) //
(build { target = "zc706"; variant = "nist_clock_satellite"; }) //
(build { target = "zc706"; variant = "nist_qc2"; }) //
(build { target = "zc706"; variant = "nist_qc2_master"; }) //
(build { target = "zc706"; variant = "nist_qc2_satellite"; }) //
(build { target = "zc706"; variant = "acpki_simple"; }) //
(build { target = "zc706"; variant = "acpki_master"; }) //
(build { target = "zc706"; variant = "acpki_satellite"; }) //
(build { target = "zc706"; variant = "acpki_nist_clock"; }) //
(build { target = "zc706"; variant = "acpki_nist_clock_master"; }) //
(build { target = "zc706"; variant = "acpki_nist_clock_satellite"; }) //

@ -1,15 +1,19 @@
TARGET := zc706
GWARGS := -V simple
GWARGS := -V nist_clock
all: ../build/runtime.bin
all: runtime
.PHONY: all
runtime: ../build/runtime.bin
satman: ../build/satman.bin
.PHONY: all runtime_target satman_target
../build/pl.rs ../build/rustc-cfg ../build/mem.rs: gateware/*
mkdir -p ../build
python gateware/$(TARGET).py -r ../build/pl.rs -c ../build/rustc-cfg -m ../build/mem.rs $(GWARGS)
../build/firmware/armv7-none-eabihf/release/runtime: ../build/pl.rs ../build/rustc-cfg ../build/mem.rs $(shell find . -print)
../build/firmware/armv7-none-eabihf/release/runtime: ../build/pl.rs ../build/rustc-cfg ../build/mem.rs $(shell find . -type f -print)
cd runtime && \
XBUILD_SYSROOT_PATH=`pwd`/../../build/sysroot \
cargo xbuild --release \
@ -19,7 +23,7 @@ all: ../build/runtime.bin
../build/runtime.bin: ../build/firmware/armv7-none-eabihf/release/runtime
llvm-objcopy -O binary ../build/firmware/armv7-none-eabihf/release/runtime ../build/runtime.bin
../build/firmware/armv7-none-eabihf/release/satman: ../build/pl.rs ../build/rustc-cfg ../build/mem.rs $(shell find . -print)
../build/firmware/armv7-none-eabihf/release/satman: ../build/pl.rs ../build/rustc-cfg ../build/mem.rs $(shell find . -type f -print)
cd satman && \
XBUILD_SYSROOT_PATH=`pwd`/../../build/sysroot \
cargo xbuild --release \

@ -426,23 +426,6 @@ class _SatelliteBase(SoCCore):
self.submodules.routing_table = rtio.RoutingTableAccess(self.cri_con)
self.csr_devices.append("routing_table")
class _Simple_RTIO:
def __init__(self):
platform = self.platform
rtio_channels = []
for i in range(4):
phy = ttl_simple.Output(platform.request("user_led", i))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
rtio_channels.append(rtio.LogChannel())
self.add_rtio(rtio_channels)
# The NIST backplanes require setting VADJ to 3.3V by reprogramming the power supply.
# This also changes the I/O standard for some on-board LEDs.
leds_fmc33 = [
@ -608,21 +591,6 @@ class _NIST_QC2_RTIO:
self.add_rtio(rtio_channels)
class Simple(ZC706, _Simple_RTIO):
def __init__(self, acpki):
ZC706.__init__(self, acpki)
_Simple_RTIO.__init__(self)
class Master(_MasterBase, _Simple_RTIO):
def __init__(self, acpki):
_MasterBase.__init__(self, acpki)
_Simple_RTIO.__init__(self)
class Satellite(_SatelliteBase, _Simple_RTIO):
def __init__(self, acpki):
_SatelliteBase.__init__(self, acpki)
_Simple_RTIO.__init__(self)
class NIST_CLOCK(ZC706, _NIST_CLOCK_RTIO):
def __init__(self, acpki):
ZC706.__init__(self, acpki)
@ -655,8 +623,7 @@ class NIST_QC2_Satellite(_SatelliteBase, _NIST_QC2_RTIO):
_NIST_QC2_RTIO.__init__(self)
VARIANTS = {cls.__name__.lower(): cls for cls in [Simple, Master, Satellite,
NIST_CLOCK, NIST_CLOCK_Master, NIST_CLOCK_Satellite,
VARIANTS = {cls.__name__.lower(): cls for cls in [NIST_CLOCK, NIST_CLOCK_Master, NIST_CLOCK_Satellite,
NIST_QC2, NIST_QC2_Master, NIST_QC2_Satellite]}
@ -691,9 +658,9 @@ def main():
help="build Rust compiler configuration into the specified file")
parser.add_argument("-g", default=None,
help="build gateware into the specified directory")
parser.add_argument("-V", "--variant", default="simple",
parser.add_argument("-V", "--variant", default="nist_clock",
help="variant: "
"[acpki_]simple/nist_clock/nist_qc2 "
"[acpki_]nist_clock/nist_qc2[_master/_satellite] "
"(default: %(default)s)")
args = parser.parse_args()

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