Merge branch 'master' into 117_rtio_channels
This commit is contained in:
commit
285b034a6b
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@ -45,7 +45,7 @@ Note: if you are using Nix channels the first time, you need to be aware of this
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Pure build with Nix and execution on a remote JTAG server:
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```shell
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nix-build -A zc706-simple-jtag # or zc706-nist_qc2-jtag or zc706-nist_clock-jtag
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nix-build -A zc706-nist_clock-jtag # or zc706-nist_qc2-jtag or zc706-nist_clock_satellite-jtag etc.
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./remote_run.sh
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```
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@ -54,8 +54,8 @@ Impure incremental build and execution on a remote JTAG server:
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```shell
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nix-shell
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cd src
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gateware/zc706.py -g ../build/gateware # build gateware
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make # build firmware
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gateware/zc706.py -g ../build/gateware -v <variant> # build gateware
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make GWARGS="-v <variant>" <runtime/satman> # build firmware
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cd ..
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./remote_run.sh -i
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```
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@ -64,6 +64,8 @@ Notes:
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- This is developed with Nixpkgs 21.05, and the ``nixbld.m-labs.hk`` binary substituter can also be used here (see the ARTIQ manual for the public key and instructions).
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- The impure build process is also compatible with non-Nix systems.
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- When calling make, you need to specify both the variant and firmware type.
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- Firmware type must be either ``runtime`` for DRTIO-less or DRTIO master variants, or ``satman`` for DRTIO satellite.
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- If the board is connected to the local machine, use the ``local_run.sh`` script.
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- To update ``zynq-rs``, update the cargo files as per usual for Rust projects, but also keep ``zynq-rs.nix`` in sync.
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18
default.nix
18
default.nix
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@ -8,7 +8,7 @@ let
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vivado = import <artiq-fast/vivado.nix> { inherit pkgs; };
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# FSBL configuration supplied by Vivado 2020.1 for these boards:
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fsblTargets = ["zc702" "zc706" "zed"];
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sat_variants = ["satellite" "acpki_satellite" "nist_clock_satellite" "nist_qc2_satellite"];
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sat_variants = ["satellite" "nist_clock_satellite" "nist_qc2_satellite" "acpki_nist_clock_satellite" "acpki_nist_qc2_satellite"];
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build = { target, variant, json ? null }: let
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szl = (import zynq-rs)."${target}-szl";
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fsbl = import "${zynq-rs}/nix/fsbl.nix" {
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@ -35,7 +35,7 @@ let
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export XARGO_RUST_SRC="${rustPlatform.rust.rustc}/lib/rustlib/src/rust/library"
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export CLANG_EXTRA_INCLUDE_DIR="${pkgs.llvmPackages_9.clang-unwrapped.lib}/lib/clang/9.0.1/include"
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export CARGO_HOME=$(mktemp -d cargo-home.XXX)
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make TARGET=${target} GWARGS="${if json == null then "-V ${variant}" else json}" ../build/${fwtype}.bin
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make TARGET=${target} GWARGS="${if json == null then "-V ${variant}" else json}" ${fwtype}
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'';
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installPhase = ''
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@ -81,14 +81,14 @@ let
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bifdir=`mktemp -d`
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cd $bifdir
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ln -s ${szl}/szl.elf szl.elf
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ln -s ${firmware}/runtime.elf runtime.elf
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ln -s ${firmware}/${fwtype}.elf ${fwtype}.elf
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ln -s ${gateware}/top.bit top.bit
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cat > boot.bif << EOF
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the_ROM_image:
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{
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[bootloader]szl.elf
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top.bit
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runtime.elf
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${fwtype}.elf
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}
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EOF
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mkdir $out $out/nix-support
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@ -106,13 +106,13 @@ let
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cd $bifdir
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ln -s ${fsbl}/fsbl.elf fsbl.elf
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ln -s ${gateware}/top.bit top.bit
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ln -s ${firmware}/runtime.elf runtime.elf
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ln -s ${firmware}/${fwtype}.elf ${fwtype}.elf
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cat > boot.bif << EOF
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the_ROM_image:
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{
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[bootloader]fsbl.elf
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top.bit
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runtime.elf
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${fwtype}.elf
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}
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EOF
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mkdir $out $out/nix-support
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@ -133,18 +133,12 @@ let
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);
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in
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(
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(build { target = "zc706"; variant = "simple"; }) //
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(build { target = "zc706"; variant = "master"; }) //
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(build { target = "zc706"; variant = "satellite"; }) //
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(build { target = "zc706"; variant = "nist_clock"; }) //
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(build { target = "zc706"; variant = "nist_clock_master"; }) //
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(build { target = "zc706"; variant = "nist_clock_satellite"; }) //
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(build { target = "zc706"; variant = "nist_qc2"; }) //
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(build { target = "zc706"; variant = "nist_qc2_master"; }) //
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(build { target = "zc706"; variant = "nist_qc2_satellite"; }) //
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(build { target = "zc706"; variant = "acpki_simple"; }) //
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(build { target = "zc706"; variant = "acpki_master"; }) //
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(build { target = "zc706"; variant = "acpki_satellite"; }) //
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(build { target = "zc706"; variant = "acpki_nist_clock"; }) //
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(build { target = "zc706"; variant = "acpki_nist_clock_master"; }) //
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(build { target = "zc706"; variant = "acpki_nist_clock_satellite"; }) //
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14
src/Makefile
14
src/Makefile
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@ -1,15 +1,19 @@
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TARGET := zc706
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GWARGS := -V simple
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GWARGS := -V nist_clock
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all: ../build/runtime.bin
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all: runtime
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.PHONY: all
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runtime: ../build/runtime.bin
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satman: ../build/satman.bin
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.PHONY: all runtime_target satman_target
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../build/pl.rs ../build/rustc-cfg ../build/mem.rs: gateware/*
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mkdir -p ../build
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python gateware/$(TARGET).py -r ../build/pl.rs -c ../build/rustc-cfg -m ../build/mem.rs $(GWARGS)
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../build/firmware/armv7-none-eabihf/release/runtime: ../build/pl.rs ../build/rustc-cfg ../build/mem.rs $(shell find . -print)
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../build/firmware/armv7-none-eabihf/release/runtime: ../build/pl.rs ../build/rustc-cfg ../build/mem.rs $(shell find . -type f -print)
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cd runtime && \
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XBUILD_SYSROOT_PATH=`pwd`/../../build/sysroot \
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cargo xbuild --release \
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@ -19,7 +23,7 @@ all: ../build/runtime.bin
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../build/runtime.bin: ../build/firmware/armv7-none-eabihf/release/runtime
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llvm-objcopy -O binary ../build/firmware/armv7-none-eabihf/release/runtime ../build/runtime.bin
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../build/firmware/armv7-none-eabihf/release/satman: ../build/pl.rs ../build/rustc-cfg ../build/mem.rs $(shell find . -print)
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../build/firmware/armv7-none-eabihf/release/satman: ../build/pl.rs ../build/rustc-cfg ../build/mem.rs $(shell find . -type f -print)
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cd satman && \
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XBUILD_SYSROOT_PATH=`pwd`/../../build/sysroot \
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cargo xbuild --release \
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@ -426,23 +426,6 @@ class _SatelliteBase(SoCCore):
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self.submodules.routing_table = rtio.RoutingTableAccess(self.cri_con)
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self.csr_devices.append("routing_table")
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class _Simple_RTIO:
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def __init__(self):
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platform = self.platform
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rtio_channels = []
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for i in range(4):
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phy = ttl_simple.Output(platform.request("user_led", i))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
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rtio_channels.append(rtio.LogChannel())
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self.add_rtio(rtio_channels)
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# The NIST backplanes require setting VADJ to 3.3V by reprogramming the power supply.
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# This also changes the I/O standard for some on-board LEDs.
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leds_fmc33 = [
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@ -608,21 +591,6 @@ class _NIST_QC2_RTIO:
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self.add_rtio(rtio_channels)
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class Simple(ZC706, _Simple_RTIO):
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def __init__(self, acpki):
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ZC706.__init__(self, acpki)
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_Simple_RTIO.__init__(self)
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class Master(_MasterBase, _Simple_RTIO):
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def __init__(self, acpki):
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_MasterBase.__init__(self, acpki)
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_Simple_RTIO.__init__(self)
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class Satellite(_SatelliteBase, _Simple_RTIO):
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def __init__(self, acpki):
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_SatelliteBase.__init__(self, acpki)
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_Simple_RTIO.__init__(self)
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class NIST_CLOCK(ZC706, _NIST_CLOCK_RTIO):
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def __init__(self, acpki):
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ZC706.__init__(self, acpki)
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@ -655,8 +623,7 @@ class NIST_QC2_Satellite(_SatelliteBase, _NIST_QC2_RTIO):
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_NIST_QC2_RTIO.__init__(self)
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VARIANTS = {cls.__name__.lower(): cls for cls in [Simple, Master, Satellite,
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NIST_CLOCK, NIST_CLOCK_Master, NIST_CLOCK_Satellite,
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VARIANTS = {cls.__name__.lower(): cls for cls in [NIST_CLOCK, NIST_CLOCK_Master, NIST_CLOCK_Satellite,
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NIST_QC2, NIST_QC2_Master, NIST_QC2_Satellite]}
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@ -691,9 +658,9 @@ def main():
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help="build Rust compiler configuration into the specified file")
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parser.add_argument("-g", default=None,
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help="build gateware into the specified directory")
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parser.add_argument("-V", "--variant", default="simple",
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parser.add_argument("-V", "--variant", default="nist_clock",
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help="variant: "
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"[acpki_]simple/nist_clock/nist_qc2 "
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"[acpki_]nist_clock/nist_qc2[_master/_satellite] "
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"(default: %(default)s)")
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args = parser.parse_args()
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