rearranged rtio for nist qc2

src/gateware/zc706.py

@@ -189,19 +189,19 @@ class NIST_CLOCK(ZC706):
         self.submodules += phy
         rtio_channels.append(rtio.Channel.from_phy(phy))
 
-        ams101_dac = self.platform.request("ams101_dac", 0)
-        phy = ttl_simple.Output(ams101_dac.ldac)
-        self.submodules += phy
-        rtio_channels.append(rtio.Channel.from_phy(phy))
+        # ams101_dac = self.platform.request("ams101_dac", 0)
+        # phy = ttl_simple.Output(ams101_dac.ldac)
+        # self.submodules += phy
+        # rtio_channels.append(rtio.Channel.from_phy(phy))
 
         phy = ttl_simple.ClockGen(platform.request("la32_p"))
         self.submodules += phy
         rtio_channels.append(rtio.Channel.from_phy(phy))
 
-        phy = spi2.SPIMaster(ams101_dac)
-        self.submodules += phy
-        rtio_channels.append(rtio.Channel.from_phy(
-            phy, ififo_depth=4))
+        # phy = spi2.SPIMaster(ams101_dac)
+        # self.submodules += phy
+        # rtio_channels.append(rtio.Channel.from_phy(
+        #     phy, ififo_depth=4))
 
         for i in range(3):
             phy = spi2.SPIMaster(self.platform.request("spi", i))
@@ -239,23 +239,36 @@ class NIST_QC2(ZC706):
 
         rtio_channels = []
 
-        for i in range(4):
-            phy = ttl_simple.Output(platform.request("user_led_33", i))
-            self.submodules += phy
-            rtio_channels.append(rtio.Channel.from_phy(phy))
-
         # All TTL channels are In+Out capable
         for i in range(40):
             phy = ttl_serdes_7series.InOut_8X(platform.request("ttl", i))
             self.submodules += phy
             rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512))
 
+        # phy = ttl_serdes_7series.InOut_8X(platform.request("user_sma_gpio_n_33"))
+        # self.submodules += phy
+        # rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512))
+
+        phy = ttl_simple.Output(platform.request("user_led_33", 2))
+        self.submodules += phy
+        rtio_channels.append(rtio.Channel.from_phy(phy))
+
+        # ams101_dac = self.platform.request("ams101_dac", 0)
+        # phy = ttl_simple.Output(ams101_dac.ldac)
+        # self.submodules += phy
+        # rtio_channels.append(rtio.Channel.from_phy(phy))
+
         # CLK0, CLK1 are for clock generators, on backplane SMP connectors
         for i in range(2):
             phy = ttl_simple.ClockGen(
                 platform.request("clkout", i))
             self.submodules += phy
             rtio_channels.append(rtio.Channel.from_phy(phy))
+        
+        # phy = spi2.SPIMaster(ams101_dac)
+        # self.submodules += phy
+        # rtio_channels.append(rtio.Channel.from_phy(
+        #     phy, ififo_depth=4))
 
         for i in range(4):
             phy = spi2.SPIMaster(self.platform.request("spi", i))