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@ -11,13 +11,20 @@ from migen_axi.integration.soc_core import SoCCore |
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from migen_axi.platforms import zc706 |
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from misoc.interconnect.csr import * |
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from misoc.integration import cpu_interface |
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from misoc.cores import gpio |
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from artiq.gateware import rtio, nist_clock, nist_qc2 |
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from artiq.gateware.rtio.phy import ttl_simple, ttl_serdes_7series, dds, spi2 |
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from artiq.gateware.rtio.xilinx_clocking import RTIOClockMultiplier, fix_serdes_timing_path |
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from artiq.gateware.drtio.transceiver import gtx_7series |
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from artiq.gateware.drtio.siphaser import SiPhaser7Series |
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from artiq.gateware.drtio.rx_synchronizer import XilinxRXSynchronizer |
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from artiq.gateware.drtio import * |
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import dma |
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import analyzer |
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import acpki |
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import drtio_aux_controller |
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class RTIOCRG(Module, AutoCSR): |
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@ -64,23 +71,45 @@ class RTIOCRG(Module, AutoCSR): |
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] |
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# The NIST backplanes require setting VADJ to 3.3V by reprogramming the power supply. |
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# This also changes the I/O standard for some on-board LEDs. |
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leds_fmc33 = [ |
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("user_led_33", 0, Pins("Y21"), IOStandard("LVCMOS33")), |
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("user_led_33", 1, Pins("G2"), IOStandard("LVCMOS15")), |
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("user_led_33", 2, Pins("W21"), IOStandard("LVCMOS33")), |
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("user_led_33", 3, Pins("A17"), IOStandard("LVCMOS15")), |
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] |
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# same deal as with LEDs - changed I/O standard. |
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si5324_fmc33 = [ |
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("si5324_33", 0, |
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Subsignal("rst_n", Pins("W23"), IOStandard("LVCMOS33")), |
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Subsignal("int", Pins("AJ25"), IOStandard("LVCMOS33")) |
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), |
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] |
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def prepare_zc706_platform(platform): |
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platform.toolchain.bitstream_commands.extend([ |
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"set_property BITSTREAM.GENERAL.COMPRESS True [current_design]", |
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]) |
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platform.add_platform_command("create_clock -name clk_fpga_0 -period 8 [get_pins \"PS7/FCLKCLK[0]\"]") |
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platform.add_platform_command("set_input_jitter clk_fpga_0 0.24") |
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class ZC706(SoCCore): |
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def __init__(self, acpki=False): |
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self.acpki = acpki |
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self.rustc_cfg = dict() |
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platform = zc706.Platform() |
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platform.toolchain.bitstream_commands.extend([ |
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"set_property BITSTREAM.GENERAL.COMPRESS True [current_design]", |
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]) |
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prepare_zc706_platform(platform) |
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ident = self.__class__.__name__ |
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if self.acpki: |
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ident = "acpki_" + ident |
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SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident) |
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platform.add_platform_command("create_clock -name clk_fpga_0 -period 8 [get_pins \"PS7/FCLKCLK[0]\"]") |
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platform.add_platform_command("set_input_jitter clk_fpga_0 0.24") |
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self.submodules.rtio_crg = RTIOCRG(self.platform, self.ps7.cd_sys.clk) |
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self.csr_devices.append("rtio_crg") |
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self.rustc_cfg["has_rtio_crg_clock_sel"] = None |
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@ -122,10 +151,284 @@ class ZC706(SoCCore): |
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self.csr_devices.append("rtio_analyzer") |
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class Simple(ZC706): |
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def __init__(self, **kwargs): |
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ZC706.__init__(self, **kwargs) |
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class _MasterBase(SoCCore): |
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def __init__(self, acpki=False): |
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self.acpki = acpki |
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self.rustc_cfg = dict() |
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platform = zc706.Platform() |
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prepare_zc706_platform(platform) |
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ident = self.__class__.__name__ |
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if self.acpki: |
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ident = "acpki_" + ident |
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SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident) |
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platform.add_extension(si5324_fmc33) |
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self.sys_clk_freq = 125e6 |
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platform = self.platform |
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self.comb += platform.request("sfp_tx_disable_n").eq(1) |
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data_pads = [ |
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platform.request("sfp"), |
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platform.request("user_sma_mgt") |
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] |
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# 1000BASE_BX10 Ethernet compatible, 125MHz RTIO clock |
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self.submodules.drtio_transceiver = gtx_7series.GTX( |
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clock_pads=platform.request("si5324_clkout"), |
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pads=data_pads, |
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sys_clk_freq=self.sys_clk_freq) |
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self.csr_devices.append("drtio_transceiver") |
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self.submodules.rtio_tsc = rtio.TSC("async", glbl_fine_ts_width=3) |
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drtio_csr_group = [] |
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drtioaux_csr_group = [] |
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drtioaux_memory_group = [] |
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self.drtio_cri = [] |
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for i in range(len(self.drtio_transceiver.channels)): |
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core_name = "drtio" + str(i) |
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coreaux_name = "drtioaux" + str(i) |
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memory_name = "drtioaux" + str(i) + "_mem" |
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drtio_csr_group.append(core_name) |
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drtioaux_csr_group.append(coreaux_name) |
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drtioaux_memory_group.append(memory_name) |
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cdr = ClockDomainsRenamer({"rtio_rx": "rtio_rx" + str(i)}) |
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core = cdr(DRTIOMaster( |
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self.rtio_tsc, self.drtio_transceiver.channels[i])) |
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setattr(self.submodules, core_name, core) |
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self.drtio_cri.append(core.cri) |
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self.csr_devices.append(core_name) |
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coreaux = cdr(drtio_aux_controller.DRTIOAuxControllerBare(core.link_layer)) |
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setattr(self.submodules, coreaux_name, coreaux) |
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self.csr_devices.append(coreaux_name) |
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mem_size = coreaux.get_mem_size() |
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memory_address = self.axi2csr.register_port(coreaux.get_tx_port(), mem_size) |
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self.axi2csr.register_port(coreaux.get_rx_port(), mem_size) |
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self.add_memory_region(memory_name, self.mem_map["csr"] + memory_address, mem_size * 2) |
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self.rustc_cfg["has_drtio"] = None |
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self.rustc_cfg["has_drtio_routing"] = None |
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self.add_csr_group("drtio", drtio_csr_group) |
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self.add_csr_group("drtioaux", drtioaux_csr_group) |
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self.add_memory_group("drtioaux_mem", drtioaux_memory_group) |
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self.rustc_cfg["RTIO_FREQUENCY"] = str(self.drtio_transceiver.rtio_clk_freq/1e6) |
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self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("si5324_33").rst_n) |
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self.csr_devices.append("si5324_rst_n") |
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self.rustc_cfg["has_si5324"] = None |
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self.rustc_cfg["si5324_as_synthesizer"] = None |
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rtio_clk_period = 1e9/self.drtio_transceiver.rtio_clk_freq |
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# Constrain TX & RX timing for the first transceiver channel |
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# (First channel acts as master for phase alignment for all channels' TX) |
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gtx0 = self.drtio_transceiver.gtxs[0] |
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platform.add_period_constraint(gtx0.txoutclk, rtio_clk_period) |
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platform.add_period_constraint(gtx0.rxoutclk, rtio_clk_period) |
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platform.add_false_path_constraints( |
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self.ps7.cd_sys.clk, |
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gtx0.txoutclk, gtx0.rxoutclk) |
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# Constrain RX timing for the each transceiver channel |
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# (Each channel performs single-lane phase alignment for RX) |
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for gtx in self.drtio_transceiver.gtxs[1:]: |
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platform.add_period_constraint(gtx.rxoutclk, rtio_clk_period) |
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platform.add_false_path_constraints( |
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self.ps7.cd_sys.clk, gtx0.txoutclk, gtx.rxoutclk) |
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self.submodules.rtio_crg = RTIOClockMultiplier(self.sys_clk_freq) |
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self.csr_devices.append("rtio_crg") |
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fix_serdes_timing_path(self.platform) |
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def add_rtio(self, rtio_channels): |
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self.submodules.rtio_tsc = rtio.TSC("async", glbl_fine_ts_width=3) |
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self.submodules.rtio_core = rtio.Core(self.rtio_tsc, rtio_channels) |
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self.csr_devices.append("rtio_core") |
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if self.acpki: |
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self.rustc_cfg["ki_impl"] = "acp" |
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self.submodules.rtio = acpki.KernelInitiator(self.rtio_tsc, |
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bus=self.ps7.s_axi_acp, |
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user=self.ps7.s_axi_acp_user, |
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evento=self.ps7.event.o) |
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self.csr_devices.append("rtio") |
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else: |
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self.rustc_cfg["ki_impl"] = "csr" |
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self.submodules.rtio = rtio.KernelInitiator(self.rtio_tsc, now64=True) |
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self.csr_devices.append("rtio") |
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self.submodules.rtio_dma = dma.DMA(self.ps7.s_axi_hp0) |
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self.csr_devices.append("rtio_dma") |
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self.submodules.local_io = SyncRTIO(self.rtio_tsc, rtio_channels) |
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self.submodules.cri_con = rtio.CRIInterconnectShared( |
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[self.rtio.cri, self.rtio_dma.cri], |
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[self.local_io.cri] + self.drtio_cri, |
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mode="sync", enable_routing=True) |
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self.csr_devices.append("cri_con") |
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self.submodules.rtio_moninj = rtio.MonInj(rtio_channels) |
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self.csr_devices.append("rtio_moninj") |
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self.submodules.rtio_analyzer = analyzer.Analyzer(self.rtio_tsc, self.rtio_core.cri, |
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self.ps7.s_axi_hp1) |
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self.csr_devices.append("rtio_analyzer") |
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self.submodules.routing_table = rtio.RoutingTableAccess(self.cri_con) |
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self.csr_devices.append("routing_table") |
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class _SatelliteBase(SoCCore): |
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def __init__(self, acpki=False): |
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self.acpki = acpki |
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self.rustc_cfg = dict() |
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platform = zc706.Platform() |
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prepare_zc706_platform(platform) |
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ident = self.__class__.__name__ |
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if self.acpki: |
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ident = "acpki_" + ident |
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SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident) |
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platform.add_extension(si5324_fmc33) |
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self.sys_clk_freq = 125e6 |
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platform = self.platform |
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# SFP |
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self.comb += platform.request("sfp_tx_disable_n").eq(0) |
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data_pads = [ |
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platform.request("sfp"), |
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platform.request("user_sma_mgt") |
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] |
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self.submodules.rtio_tsc = rtio.TSC("sync", glbl_fine_ts_width=3) |
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# 1000BASE_BX10 Ethernet compatible, 125MHz RTIO clock |
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self.submodules.drtio_transceiver = gtx_7series.GTX( |
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clock_pads=platform.request("si5324_clkout"), |
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pads=data_pads, |
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sys_clk_freq=self.sys_clk_freq) |
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self.csr_devices.append("drtio_transceiver") |
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drtioaux_csr_group = [] |
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drtioaux_memory_group = [] |
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drtiorep_csr_group = [] |
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self.drtio_cri = [] |
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for i in range(len(self.drtio_transceiver.channels)): |
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coreaux_name = "drtioaux" + str(i) |
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memory_name = "drtioaux" + str(i) + "_mem" |
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drtioaux_csr_group.append(coreaux_name) |
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drtioaux_memory_group.append(memory_name) |
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cdr = ClockDomainsRenamer({"rtio_rx": "rtio_rx" + str(i)}) |
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# Satellite |
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if i == 0: |
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self.submodules.rx_synchronizer = cdr(XilinxRXSynchronizer()) |
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core = cdr(DRTIOSatellite( |
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self.rtio_tsc, self.drtio_transceiver.channels[0], self.rx_synchronizer)) |
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self.submodules.drtiosat = core |
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self.csr_devices.append("drtiosat") |
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# Repeaters |
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else: |
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corerep_name = "drtiorep" + str(i-1) |
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drtiorep_csr_group.append(corerep_name) |
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core = cdr(DRTIORepeater( |
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self.rtio_tsc, self.drtio_transceiver.channels[i])) |
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setattr(self.submodules, corerep_name, core) |
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self.drtio_cri.append(core.cri) |
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self.csr_devices.append(corerep_name) |
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coreaux = cdr(drtio_aux_controller.DRTIOAuxControllerBare(core.link_layer)) |
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setattr(self.submodules, coreaux_name, coreaux) |
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self.csr_devices.append(coreaux_name) |
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mem_size = coreaux.get_mem_size() |
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tx_port = coreaux.get_tx_port() |
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rx_port = coreaux.get_rx_port() |
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memory_address = self.axi2csr.register_port(tx_port, mem_size) |
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# rcv in upper half of the memory, thus added second |
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self.axi2csr.register_port(rx_port, mem_size) |
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# and registered in PS interface |
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# manually, because software refers to rx/tx by halves of entire memory block, not names |
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self.add_memory_region(memory_name, self.mem_map["csr"] + memory_address, mem_size * 2) |
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self.rustc_cfg["has_drtio"] = None |
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self.rustc_cfg["has_drtio_routing"] = None |
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self.add_csr_group("drtioaux", drtioaux_csr_group) |
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self.add_csr_group("drtiorep", drtiorep_csr_group) |
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self.add_memory_group("drtioaux_mem", drtioaux_memory_group) |
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self.rustc_cfg["rtio_frequency"] = str(self.drtio_transceiver.rtio_clk_freq/1e6) |
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# Si5324 Phaser |
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self.submodules.siphaser = SiPhaser7Series( |
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si5324_clkin=platform.request("si5324_clkin"), |
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rx_synchronizer=self.rx_synchronizer, |
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ultrascale=False, |
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rtio_clk_freq=self.drtio_transceiver.rtio_clk_freq) |
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platform.add_false_path_constraints( |
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self.ps7.cd_sys.clk, self.siphaser.mmcm_freerun_output) |
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self.csr_devices.append("siphaser") |
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self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("si5324_33").rst_n) |
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self.csr_devices.append("si5324_rst_n") |
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self.rustc_cfg["has_si5324"] = None |
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self.rustc_cfg["has_siphaser"] = None |
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rtio_clk_period = 1e9/self.drtio_transceiver.rtio_clk_freq |
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# Constrain TX & RX timing for the first transceiver channel |
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# (First channel acts as master for phase alignment for all channels' TX) |
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gtx0 = self.drtio_transceiver.gtxs[0] |
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platform.add_period_constraint(gtx0.txoutclk, rtio_clk_period) |
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platform.add_period_constraint(gtx0.rxoutclk, rtio_clk_period) |
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platform.add_false_path_constraints( |
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self.ps7.cd_sys.clk, |
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gtx0.txoutclk, gtx0.rxoutclk) |
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# Constrain RX timing for the each transceiver channel |
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# (Each channel performs single-lane phase alignment for RX) |
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for gtx in self.drtio_transceiver.gtxs[1:]: |
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platform.add_period_constraint(gtx.rxoutclk, rtio_clk_period) |
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platform.add_false_path_constraints( |
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self.ps7.cd_sys.clk, gtx.rxoutclk) |
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self.submodules.rtio_crg = RTIOClockMultiplier(self.sys_clk_freq) |
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self.csr_devices.append("rtio_crg") |
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fix_serdes_timing_path(self.platform) |
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def add_rtio(self, rtio_channels): |
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self.submodules.rtio_moninj = rtio.MonInj(rtio_channels) |
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self.csr_devices.append("rtio_moninj") |
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if self.acpki: |
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self.rustc_cfg["ki_impl"] = "acp" |
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self.submodules.rtio = acpki.KernelInitiator(self.rtio_tsc, |
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bus=self.ps7.s_axi_acp, |
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user=self.ps7.s_axi_acp_user, |
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evento=self.ps7.event.o) |
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self.csr_devices.append("rtio") |
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else: |
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self.rustc_cfg["ki_impl"] = "csr" |
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self.submodules.rtio = rtio.KernelInitiator(self.rtio_tsc, now64=True) |
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self.csr_devices.append("rtio") |
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self.submodules.local_io = SyncRTIO(self.rtio_tsc, rtio_channels) |
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self.submodules.cri_con = rtio.CRIInterconnectShared( |
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[self.drtiosat.cri], |
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[self.local_io.cri] + self.drtio_cri, |
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mode="sync", enable_routing=True) |
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self.csr_devices.append("cri_con") |
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self.submodules.routing_table = rtio.RoutingTableAccess(self.cri_con) |
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self.csr_devices.append("routing_table") |
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class _Simple_RTIO: |
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def __init__(self): |
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platform = self.platform |
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rtio_channels = [] |
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@ -170,13 +473,11 @@ _sdcard_spi_33 = [ |
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) |
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] |
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class NIST_CLOCK(ZC706): |
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class _NIST_CLOCK_RTIO: |
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""" |
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NIST clock hardware, with old backplane and 11 DDS channels |
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""" |
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def __init__(self, **kwargs): |
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ZC706.__init__(self, **kwargs) |
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def __init__(self): |
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platform = self.platform |
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platform.add_extension(nist_clock.fmc_adapter_io) |
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platform.add_extension(leds_fmc33) |
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@ -245,14 +546,12 @@ class NIST_CLOCK(ZC706): |
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self.add_rtio(rtio_channels) |
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class NIST_QC2(ZC706): |
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class _NIST_QC2_RTIO: |
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""" |
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NIST QC2 hardware, as used in Quantum I and Quantum II, with new backplane |
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and 24 DDS channels. Two backplanes are used. |
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""" |
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def __init__(self, **kwargs): |
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ZC706.__init__(self, **kwargs) |
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def __init__(self): |
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platform = self.platform |
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platform.add_extension(nist_qc2.fmc_adapter_io) |
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platform.add_extension(leds_fmc33) |
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@ -309,7 +608,56 @@ class NIST_QC2(ZC706): |
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self.add_rtio(rtio_channels) |
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VARIANTS = {cls.__name__.lower(): cls for cls in [Simple, NIST_CLOCK, NIST_QC2]} |
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class Simple(ZC706, _Simple_RTIO): |
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def __init__(self, acpki): |
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ZC706.__init__(self, acpki) |
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_Simple_RTIO.__init__(self) |
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class Master(_MasterBase, _Simple_RTIO): |
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def __init__(self, acpki): |
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_MasterBase.__init__(self, acpki) |
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_Simple_RTIO.__init__(self) |
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class Satellite(_SatelliteBase, _Simple_RTIO): |
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def __init__(self, acpki): |
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_SatelliteBase.__init__(self, acpki) |
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_Simple_RTIO.__init__(self) |
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class NIST_CLOCK(ZC706, _NIST_CLOCK_RTIO): |
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def __init__(self, acpki): |
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ZC706.__init__(self, acpki) |
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|
_NIST_CLOCK_RTIO.__init__(self) |
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class NIST_CLOCK_Master(_MasterBase, _NIST_CLOCK_RTIO): |
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def __init__(self, acpki): |
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_MasterBase.__init__(self, acpki) |
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|
_NIST_CLOCK_RTIO.__init__(self) |
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class NIST_CLOCK_Satellite(_SatelliteBase, _NIST_CLOCK_RTIO): |
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|
def __init__(self, acpki): |
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|
|
_SatelliteBase.__init__(self, acpki) |
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|
|
_NIST_CLOCK_RTIO.__init__(self) |
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|
|
class NIST_QC2(ZC706, _NIST_QC2_RTIO): |
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|
|
def __init__(self, acpki): |
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|
|
ZC706.__init__(self, acpki) |
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|
|
_NIST_QC2_RTIO.__init__(self) |
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|
class NIST_QC2_Master(_MasterBase, _NIST_QC2_RTIO): |
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|
|
def __init__(self, acpki): |
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|
|
_MasterBase.__init__(self, acpki) |
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|
|
_NIST_QC2_RTIO.__init__(self) |
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|
|
class NIST_QC2_Satellite(_SatelliteBase, _NIST_QC2_RTIO): |
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|
def __init__(self, acpki): |
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|
|
_SatelliteBase.__init__(self, acpki) |
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|
|
_NIST_QC2_RTIO.__init__(self) |
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|
VARIANTS = {cls.__name__.lower(): cls for cls in [Simple, Master, Satellite, |
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|
|
NIST_CLOCK, NIST_CLOCK_Master, NIST_CLOCK_Satellite, |
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|
|
NIST_QC2, NIST_QC2_Master, NIST_QC2_Satellite]} |
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|
def write_csr_file(soc, filename): |
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|
|
@ -317,6 +665,11 @@ def write_csr_file(soc, filename): |
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|
|
f.write(cpu_interface.get_csr_rust( |
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|
|
soc.get_csr_regions(), soc.get_csr_groups(), soc.get_constants())) |
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|
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|
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|
|
def write_mem_file(soc, filename): |
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|
|
with open(filename, "w") as f: |
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|
|
f.write(cpu_interface.get_mem_rust( |
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|
|
soc.get_memory_regions(), soc.get_memory_groups(), None)) |
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|
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|
|
|
def write_rustc_cfg_file(soc, filename): |
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|
|
with open(filename, "w") as f: |
|
|
|
@ -332,6 +685,8 @@ def main(): |
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|
|
|
description="ARTIQ port to the ZC706 Zynq development kit") |
|
|
|
|
parser.add_argument("-r", default=None, |
|
|
|
|
help="build Rust interface into the specified file") |
|
|
|
|
parser.add_argument("-m", default=None, |
|
|
|
|
help="build Rust memory interface into the specified file") |
|
|
|
|
parser.add_argument("-c", default=None, |
|
|
|
|
help="build Rust compiler configuration into the specified file") |
|
|
|
|
parser.add_argument("-g", default=None, |
|
|
|
@ -356,11 +711,12 @@ def main(): |
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|
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|
|
if args.r is not None: |
|
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|
|
write_csr_file(soc, args.r) |
|
|
|
|
if args.m is not None: |
|
|
|
|
write_mem_file(soc, args.m) |
|
|
|
|
if args.c is not None: |
|
|
|
|
write_rustc_cfg_file(soc, args.c) |
|
|
|
|
if args.g is not None: |
|
|
|
|
soc.build(build_dir=args.g) |
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|
|
|
|
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|
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|
|
|
|
|
|
if __name__ == "__main__": |
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|
|
main() |
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|
|