Commit Graph

9 Commits

Author SHA1 Message Date
353b34a135 implement UART, Timer, SPI Flash & Eth RGMII cores
* These implementations use Harry's proposal for nmigen-stdio & nmigen-soc
2020-03-02 19:55:22 +08:00
70638e6d87 add wishbone components 2019-05-02 12:53:08 +08:00
88db84cfd7 uart: style 2019-05-02 12:52:29 +08:00
d765dfb7b9 add __all__ 2019-05-01 17:05:19 +08:00
a19f0784d0 use Elaboratable 2019-04-26 16:57:59 +08:00
2bd819fcbe roundrobin: use nmigen zero-width signals 2019-04-18 11:58:51 +08:00
e14031fba6 add round-robin arbiter 2019-04-17 20:18:41 +08:00
3dd10e6b9b add simple test for UART 2019-03-28 19:39:30 +08:00
55e12d3185 add component library with UART 2019-03-19 16:52:02 +08:00