mwojcik
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8ab2b3f299
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aux_controller: connect r/w/b lanes to axi bus
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2021-09-29 11:50:52 +02:00 |
mwojcik
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9c09216281
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updated gateware for not yet published migen-axi changes
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2021-09-13 15:06:34 +02:00 |
mwojcik
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d3152f3d24
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changed auxctrl tx/rx memory to axi2csr_sram
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2021-09-10 15:25:05 +02:00 |
mwojcik
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b2d9003d9f
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drtioaucontroller: made two decoders
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2021-08-20 15:13:56 +02:00 |
mwojcik
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e43684a3ed
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moved AXI SRAM to migen-axi
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2021-08-18 12:36:17 +02:00 |
mwojcik
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7b868e1c9d
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few fixes, typos and missed unnecessary statements
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2021-08-17 13:16:02 +02:00 |
mwojcik
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61f81cec47
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sram: redesigned write FSM. removed unused signals
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2021-08-17 11:10:08 +02:00 |
mwojcik
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3e1d14ff38
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replaced increment logic with ready Incr module
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2021-08-16 15:33:50 +02:00 |
mwojcik
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67ed7fae78
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sram: or operator in wrong place for wrapped burst
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2021-08-16 12:05:23 +02:00 |
mwojcik
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f015d6732b
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sram: support for different burst settings on read
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2021-08-16 11:51:50 +02:00 |
mwojcik
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b6dd5bea68
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sram: fixed wrong assumptions on some signals
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2021-08-13 14:58:18 +02:00 |
mwojcik
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bfe0c34f57
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sram: rewrote read fsm for sram
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2021-08-13 14:14:43 +02:00 |
mwojcik
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39509f01d6
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aux_controller: sram ported to axi, first attempt
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2021-08-13 13:06:10 +02:00 |
mwojcik
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066987bf07
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aux_controller: started porting from wb to axi
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2021-08-11 14:34:44 +02:00 |