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artiq/artiq/gateware
Robert Jördens f8e6b4f4e3 ad5360: port to spi2
* kc705 nist_clock target gateware
* coredevice driver
* moninj code
* test/example/device_db

This is untested as we don't have a AD5360 board right now.
Will be tested with Zotino v1.1

m-labs/artiq#926
2018-02-22 10:25:46 +01:00
..
amp refactor targets 2018-01-22 18:25:10 +08:00
drtio drtio: reorganize RX synchronizers 2018-02-22 15:21:23 +08:00
dsp Revert "sawg: advance dds 1/2 by one sample group" 2017-07-04 17:55:19 +02:00
rtio ad5360: port to spi2 2018-02-22 10:25:46 +01:00
serwb serwb/phy: get 625Mbps linerate working, increase timeout 2018-01-09 18:54:52 +01:00
targets ad5360: port to spi2 2018-02-22 10:25:46 +01:00
test drtio: fix test infinite loop 2018-02-20 17:42:00 +08:00
__init__.py artiqlib -> artiq.gateware 2015-03-08 11:00:24 +01:00
ad9_dds.py ad9xxx -> ad9_dds 2017-01-04 11:34:52 +01:00
nist_clock.py gateware/nist_clock: increase DDS bus drive strength. Closes #468 2016-06-07 11:08:19 -04:00
nist_qc2.py qc2: swap SPI/TTL, all TTL lines are now In+Out compatible 2016-05-19 10:42:03 +08:00
remote_csr.py remote_csr: add sanity check of CSR CSV type column 2018-02-13 20:02:51 +08:00
spi.py spi: add diff_term, save power on outputs 2018-01-02 13:20:47 +01:00