forked from M-Labs/artiq
drtio: fix test infinite loop
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@ -68,6 +68,10 @@ class DUT(Module):
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self.submodules.satellite = DRTIOSatellite(
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self.transceivers.bob, rtio_channels, rx_synchronizer,
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lane_count=4, fifo_depth=8, fine_ts_width=0)
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self.satellite.reset.storage.reset = 0
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self.satellite.reset.storage_full.reset = 0
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self.satellite.reset_phy.storage.reset = 0
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self.satellite.reset_phy.storage_full.reset = 0
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class OutputsTestbench:
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