forked from M-Labs/artiq
ad9xxx -> ad9_dds
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52fda27cb5
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@ -4,7 +4,7 @@ from migen.genlib.misc import WaitTimer
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from misoc.interconnect import wishbone
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class AD9xxx(Module):
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class AD9_DDS(Module):
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"""Wishbone interface to the AD9858 and AD9914 DDS chips.
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Addresses 0-2**len(pads.a)-1 map the AD9xxx registers.
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@ -178,5 +178,5 @@ class _TestPads:
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if __name__ == "__main__":
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pads = _TestPads()
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dut = AD9xxx(pads)
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run_simulation(dut, _test_gen(dut.bus), vcd_name="ad9xxx.vcd")
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dut = AD9_DDS(pads)
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run_simulation(dut, _test_gen(dut.bus), vcd_name="ad9_dds.vcd")
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@ -1,13 +1,13 @@
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from migen import *
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from artiq.gateware import ad9xxx
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from artiq.gateware import ad9_dds
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from artiq.gateware.rtio.phy.wishbone import RT2WB
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class _AD9xxx(Module):
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class _AD9_DDS(Module):
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def __init__(self, ftw_base, pads, nchannels, onehot=False, **kwargs):
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self.submodules._ll = ClockDomainsRenamer("rio_phy")(
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ad9xxx.AD9xxx(pads, **kwargs))
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ad9_dds.AD9_DDS(pads, **kwargs))
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self.submodules._rt2wb = RT2WB(len(pads.a)+1, self._ll.bus)
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self.rtlink = self._rt2wb.rtlink
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self.probes = [Signal(32) for i in range(nchannels)]
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@ -56,6 +56,6 @@ class _AD9xxx(Module):
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for c, (probe, ftw) in enumerate(zip(self.probes, ftws))])
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class AD9914(_AD9xxx):
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class AD9914(_AD9_DDS):
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def __init__(self, *args, **kwargs):
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_AD9xxx.__init__(self, 0x2d, *args, **kwargs)
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_AD9_DDS.__init__(self, 0x2d, *args, **kwargs)
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